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4vtomat4vtomat
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fixup! Rename matmul operand
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18 files changed

+88
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‎clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -7,12 +7,12 @@
77
#include <sifive_vector.h>
88

99
// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_e4m3_e4m3_w4_u8m8_u8m8(
10-
// CHECK-RV64-SAME: <vscale x 64 x i8> [[V1:%.*]], <vscale x 64 x i8> [[V2:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] {
10+
// CHECK-RV64-SAME: <vscale x 64 x i8> [[vs2:%.*]], <vscale x 64 x i8> [[vs1:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] {
1111
// CHECK-RV64-NEXT: entry:
12-
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.e4m3.e4m3.i64.nxv64i8(i64 0, <vscale x 64 x i8> [[V1]], <vscale x 64 x i8> [[V2]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 4)
12+
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.e4m3.e4m3.i64.nxv64i8(i64 0, <vscale x 64 x i8> [[vs2]], <vscale x 64 x i8> [[vs1]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 4)
1313
// CHECK-RV64-NEXT: ret void
1414
//
15-
void test_sf_mm_e4m3_e4m3_w4_u8m8_u8m8(vuint8m8_t v1, vuint8m8_t v2, size_t tm, size_t tn, size_t tk) {
16-
return __riscv_sf_mm_e4m3_e4m3_w4_u8m8_u8m8(0, v1, v2, tm, tn, tk);
15+
void test_sf_mm_e4m3_e4m3_w4_u8m8_u8m8(vuint8m8_t vs2, vuint8m8_t vs1, size_t tm, size_t tn, size_t tk) {
16+
return __riscv_sf_mm_e4m3_e4m3_w4_u8m8_u8m8(0, vs2, vs1, tm, tn, tk);
1717
}
1818

‎clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -7,12 +7,12 @@
77
#include <sifive_vector.h>
88

99
// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_e4m3_e5m2_w4_u8m8_u8m8(
10-
// CHECK-RV64-SAME: <vscale x 64 x i8> [[V1:%.*]], <vscale x 64 x i8> [[V2:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] {
10+
// CHECK-RV64-SAME: <vscale x 64 x i8> [[vs2:%.*]], <vscale x 64 x i8> [[vs1:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] {
1111
// CHECK-RV64-NEXT: entry:
12-
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.e4m3.e5m2.i64.nxv64i8(i64 0, <vscale x 64 x i8> [[V1]], <vscale x 64 x i8> [[V2]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 4)
12+
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.e4m3.e5m2.i64.nxv64i8(i64 0, <vscale x 64 x i8> [[vs2]], <vscale x 64 x i8> [[vs1]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 4)
1313
// CHECK-RV64-NEXT: ret void
1414
//
15-
void test_sf_mm_e4m3_e5m2_w4_u8m8_u8m8(vuint8m8_t v1, vuint8m8_t v2, size_t tm, size_t tn, size_t tk) {
16-
return __riscv_sf_mm_e4m3_e5m2_w4_u8m8_u8m8(0, v1, v2, tm, tn, tk);
15+
void test_sf_mm_e4m3_e5m2_w4_u8m8_u8m8(vuint8m8_t vs2, vuint8m8_t vs1, size_t tm, size_t tn, size_t tk) {
16+
return __riscv_sf_mm_e4m3_e5m2_w4_u8m8_u8m8(0, vs2, vs1, tm, tn, tk);
1717
}
1818

‎clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -7,12 +7,12 @@
77
#include <sifive_vector.h>
88

99
// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_e5m2_e4m3_w4_u8m8_u8m8(
10-
// CHECK-RV64-SAME: <vscale x 64 x i8> [[V1:%.*]], <vscale x 64 x i8> [[V2:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] {
10+
// CHECK-RV64-SAME: <vscale x 64 x i8> [[vs2:%.*]], <vscale x 64 x i8> [[vs1:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] {
1111
// CHECK-RV64-NEXT: entry:
12-
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.e5m2.e4m3.i64.nxv64i8(i64 0, <vscale x 64 x i8> [[V1]], <vscale x 64 x i8> [[V2]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 4)
12+
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.e5m2.e4m3.i64.nxv64i8(i64 0, <vscale x 64 x i8> [[vs2]], <vscale x 64 x i8> [[vs1]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 4)
1313
// CHECK-RV64-NEXT: ret void
1414
//
15-
void test_sf_mm_e5m2_e4m3_w4_u8m8_u8m8(vuint8m8_t v1, vuint8m8_t v2, size_t tm, size_t tn, size_t tk) {
16-
return __riscv_sf_mm_e5m2_e4m3_w4_u8m8_u8m8(0, v1, v2, tm, tn, tk);
15+
void test_sf_mm_e5m2_e4m3_w4_u8m8_u8m8(vuint8m8_t vs2, vuint8m8_t vs1, size_t tm, size_t tn, size_t tk) {
16+
return __riscv_sf_mm_e5m2_e4m3_w4_u8m8_u8m8(0, vs2, vs1, tm, tn, tk);
1717
}
1818

‎clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -7,12 +7,12 @@
77
#include <sifive_vector.h>
88

99
// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_e5m2_e5m2_w4_u8m8_u8m8(
10-
// CHECK-RV64-SAME: <vscale x 64 x i8> [[V1:%.*]], <vscale x 64 x i8> [[V2:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] {
10+
// CHECK-RV64-SAME: <vscale x 64 x i8> [[vs2:%.*]], <vscale x 64 x i8> [[vs1:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] {
1111
// CHECK-RV64-NEXT: entry:
12-
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.e5m2.e5m2.i64.nxv64i8(i64 0, <vscale x 64 x i8> [[V1]], <vscale x 64 x i8> [[V2]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 4)
12+
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.e5m2.e5m2.i64.nxv64i8(i64 0, <vscale x 64 x i8> [[vs2]], <vscale x 64 x i8> [[vs1]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 4)
1313
// CHECK-RV64-NEXT: ret void
1414
//
15-
void test_sf_mm_e5m2_e5m2_w4_u8m8_u8m8(vuint8m8_t v1, vuint8m8_t v2, size_t tm, size_t tn, size_t tk) {
16-
return __riscv_sf_mm_e5m2_e5m2_w4_u8m8_u8m8(0, v1, v2, tm, tn, tk);
15+
void test_sf_mm_e5m2_e5m2_w4_u8m8_u8m8(vuint8m8_t vs2, vuint8m8_t vs1, size_t tm, size_t tn, size_t tk) {
16+
return __riscv_sf_mm_e5m2_e5m2_w4_u8m8_u8m8(0, vs2, vs1, tm, tn, tk);
1717
}
1818

‎clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -9,32 +9,32 @@
99
#include <sifive_vector.h>
1010

1111
// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_f_f_w2_f16m8(
12-
// CHECK-RV64-SAME: <vscale x 32 x half> [[V1:%.*]], <vscale x 32 x half> [[V2:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] {
12+
// CHECK-RV64-SAME: <vscale x 32 x half> [[vs2:%.*]], <vscale x 32 x half> [[vs1:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] {
1313
// CHECK-RV64-NEXT: entry:
14-
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 0, <vscale x 32 x half> [[V1]], <vscale x 32 x half> [[V2]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 2)
14+
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 0, <vscale x 32 x half> [[vs2]], <vscale x 32 x half> [[vs1]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 2)
1515
// CHECK-RV64-NEXT: ret void
1616
//
17-
void test_sf_mm_f_f_w2_f16m8(vfloat16m8_t v1, vfloat16m8_t v2, size_t tm, size_t tn, size_t tk) {
18-
return __riscv_sf_mm_f_f_w2_f16m8(0, v1, v2, tm, tn, tk);
17+
void test_sf_mm_f_f_w2_f16m8(vfloat16m8_t vs2, vfloat16m8_t vs1, size_t tm, size_t tn, size_t tk) {
18+
return __riscv_sf_mm_f_f_w2_f16m8(0, vs2, vs1, tm, tn, tk);
1919
}
2020

2121
// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_f_f_w1_f32m8(
22-
// CHECK-RV64-SAME: <vscale x 16 x float> [[V1:%.*]], <vscale x 16 x float> [[V2:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0]] {
22+
// CHECK-RV64-SAME: <vscale x 16 x float> [[vs2:%.*]], <vscale x 16 x float> [[vs1:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0]] {
2323
// CHECK-RV64-NEXT: entry:
24-
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.f.f.i64.nxv16f32(i64 0, <vscale x 16 x float> [[V1]], <vscale x 16 x float> [[V2]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 1)
24+
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.f.f.i64.nxvs26f32(i64 0, <vscale x 16 x float> [[vs2]], <vscale x 16 x float> [[vs1]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 1)
2525
// CHECK-RV64-NEXT: ret void
2626
//
27-
void test_sf_mm_f_f_w1_f32m8(vfloat32m8_t v1, vfloat32m8_t v2, size_t tm, size_t tn, size_t tk) {
28-
return __riscv_sf_mm_f_f_w1_f32m8(0, v1, v2, tm, tn, tk);
27+
void test_sf_mm_f_f_w1_f32m8(vfloat32m8_t vs2, vfloat32m8_t vs1, size_t tm, size_t tn, size_t tk) {
28+
return __riscv_sf_mm_f_f_w1_f32m8(0, vs2, vs1, tm, tn, tk);
2929
}
3030

3131
// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_f_f_w1_f64m8(
32-
// CHECK-RV64-SAME: <vscale x 8 x double> [[V1:%.*]], <vscale x 8 x double> [[V2:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0]] {
32+
// CHECK-RV64-SAME: <vscale x 8 x double> [[vs2:%.*]], <vscale x 8 x double> [[vs1:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0]] {
3333
// CHECK-RV64-NEXT: entry:
34-
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.f.f.i64.nxv8f64(i64 0, <vscale x 8 x double> [[V1]], <vscale x 8 x double> [[V2]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 1)
34+
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.f.f.i64.nxv8f64(i64 0, <vscale x 8 x double> [[vs2]], <vscale x 8 x double> [[vs1]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 1)
3535
// CHECK-RV64-NEXT: ret void
3636
//
37-
void test_sf_mm_f_f_w1_f64m8(vfloat64m8_t v1, vfloat64m8_t v2, size_t tm, size_t tn, size_t tk) {
38-
return __riscv_sf_mm_f_f_w1_f64m8(0, v1, v2, tm, tn, tk);
37+
void test_sf_mm_f_f_w1_f64m8(vfloat64m8_t vs2, vfloat64m8_t vs1, size_t tm, size_t tn, size_t tk) {
38+
return __riscv_sf_mm_f_f_w1_f64m8(0, vs2, vs1, tm, tn, tk);
3939
}
4040

‎clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -7,12 +7,12 @@
77
#include <sifive_vector.h>
88

99
// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_s_s_w4_i8m8_i8m8(
10-
// CHECK-RV64-SAME: <vscale x 64 x i8> [[V1:%.*]], <vscale x 64 x i8> [[V2:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] {
10+
// CHECK-RV64-SAME: <vscale x 64 x i8> [[vs2:%.*]], <vscale x 64 x i8> [[vs1:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] {
1111
// CHECK-RV64-NEXT: entry:
12-
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.s.s.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> [[V1]], <vscale x 64 x i8> [[V2]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 4)
12+
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.s.s.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> [[vs2]], <vscale x 64 x i8> [[vs1]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 4)
1313
// CHECK-RV64-NEXT: ret void
1414
//
15-
void test_sf_mm_s_s_w4_i8m8_i8m8(vint8m8_t v1, vint8m8_t v2, size_t tm, size_t tn, size_t tk) {
16-
return __riscv_sf_mm_s_s_w4_i8m8_i8m8(0, v1, v2, tm, tn, tk);
15+
void test_sf_mm_s_s_w4_i8m8_i8m8(vint8m8_t vs2, vint8m8_t vs1, size_t tm, size_t tn, size_t tk) {
16+
return __riscv_sf_mm_s_s_w4_i8m8_i8m8(0, vs2, vs1, tm, tn, tk);
1717
}
1818

‎clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -7,12 +7,12 @@
77
#include <sifive_vector.h>
88

99
// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_s_u_w4_i8m8_u8m8(
10-
// CHECK-RV64-SAME: <vscale x 64 x i8> [[V1:%.*]], <vscale x 64 x i8> [[V2:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] {
10+
// CHECK-RV64-SAME: <vscale x 64 x i8> [[vs2:%.*]], <vscale x 64 x i8> [[vs1:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] {
1111
// CHECK-RV64-NEXT: entry:
12-
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.s.u.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> [[V1]], <vscale x 64 x i8> [[V2]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 4)
12+
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.s.u.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> [[vs2]], <vscale x 64 x i8> [[vs1]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 4)
1313
// CHECK-RV64-NEXT: ret void
1414
//
15-
void test_sf_mm_s_u_w4_i8m8_u8m8(vint8m8_t v1, vuint8m8_t v2, size_t tm, size_t tn, size_t tk) {
16-
return __riscv_sf_mm_s_u_w4_i8m8_u8m8(0, v1, v2, tm, tn, tk);
15+
void test_sf_mm_s_u_w4_i8m8_u8m8(vint8m8_t vs2, vuint8m8_t vs1, size_t tm, size_t tn, size_t tk) {
16+
return __riscv_sf_mm_s_u_w4_i8m8_u8m8(0, vs2, vs1, tm, tn, tk);
1717
}
1818

‎clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -7,12 +7,12 @@
77
#include <sifive_vector.h>
88

99
// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_u_s_w4_u8m8_i8m8(
10-
// CHECK-RV64-SAME: <vscale x 64 x i8> [[V1:%.*]], <vscale x 64 x i8> [[V2:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] {
10+
// CHECK-RV64-SAME: <vscale x 64 x i8> [[vs2:%.*]], <vscale x 64 x i8> [[vs1:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] {
1111
// CHECK-RV64-NEXT: entry:
12-
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.u.s.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> [[V1]], <vscale x 64 x i8> [[V2]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 4)
12+
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.u.s.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> [[vs2]], <vscale x 64 x i8> [[vs1]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 4)
1313
// CHECK-RV64-NEXT: ret void
1414
//
15-
void test_sf_mm_u_s_w4_u8m8_i8m8(vuint8m8_t v1, vint8m8_t v2, size_t tm, size_t tn, size_t tk) {
16-
return __riscv_sf_mm_u_s_w4_u8m8_i8m8(0, v1, v2, tm, tn, tk);
15+
void test_sf_mm_u_s_w4_u8m8_i8m8(vuint8m8_t vs2, vint8m8_t vs1, size_t tm, size_t tn, size_t tk) {
16+
return __riscv_sf_mm_u_s_w4_u8m8_i8m8(0, vs2, vs1, tm, tn, tk);
1717
}
1818

‎clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -7,12 +7,12 @@
77
#include <sifive_vector.h>
88

99
// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_u_u_w4_u8m8_u8m8(
10-
// CHECK-RV64-SAME: <vscale x 64 x i8> [[V1:%.*]], <vscale x 64 x i8> [[V2:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] {
10+
// CHECK-RV64-SAME: <vscale x 64 x i8> [[vs2:%.*]], <vscale x 64 x i8> [[vs1:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] {
1111
// CHECK-RV64-NEXT: entry:
12-
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.u.u.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> [[V1]], <vscale x 64 x i8> [[V2]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 4)
12+
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.u.u.i64.nxv64i8.nxv64i8(i64 0, <vscale x 64 x i8> [[vs2]], <vscale x 64 x i8> [[vs1]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 4)
1313
// CHECK-RV64-NEXT: ret void
1414
//
15-
void test_sf_mm_u_u_w4_u8m8_u8m8(vuint8m8_t v1, vuint8m8_t v2, size_t tm, size_t tn, size_t tk) {
16-
return __riscv_sf_mm_u_u_w4_u8m8_u8m8(0, v1, v2, tm, tn, tk);
15+
void test_sf_mm_u_u_w4_u8m8_u8m8(vuint8m8_t vs2, vuint8m8_t vs1, size_t tm, size_t tn, size_t tk) {
16+
return __riscv_sf_mm_u_u_w4_u8m8_u8m8(0, vs2, vs1, tm, tn, tk);
1717
}
1818

‎clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -7,12 +7,12 @@
77
#include <sifive_vector.h>
88

99
// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_e4m3_e4m3_w4_u8m8_u8m8(
10-
// CHECK-RV64-SAME: <vscale x 64 x i8> [[V1:%.*]], <vscale x 64 x i8> [[V2:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] {
10+
// CHECK-RV64-SAME: <vscale x 64 x i8> [[vs2:%.*]], <vscale x 64 x i8> [[vs1:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] {
1111
// CHECK-RV64-NEXT: entry:
12-
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.e4m3.e4m3.i64.nxv64i8(i64 0, <vscale x 64 x i8> [[V1]], <vscale x 64 x i8> [[V2]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 4)
12+
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.e4m3.e4m3.i64.nxv64i8(i64 0, <vscale x 64 x i8> [[vs2]], <vscale x 64 x i8> [[vs1]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 4)
1313
// CHECK-RV64-NEXT: ret void
1414
//
15-
void test_sf_mm_e4m3_e4m3_w4_u8m8_u8m8(vuint8m8_t v1, vuint8m8_t v2, size_t tm, size_t tn, size_t tk) {
16-
return __riscv_sf_mm_e4m3_e4m3(0, v1, v2, tm, tn, tk);
15+
void test_sf_mm_e4m3_e4m3_w4_u8m8_u8m8(vuint8m8_t vs2, vuint8m8_t vs1, size_t tm, size_t tn, size_t tk) {
16+
return __riscv_sf_mm_e4m3_e4m3(0, vs2, vs1, tm, tn, tk);
1717
}
1818

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