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[DAGCombiner] Update lit test.
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‎llvm/test/CodeGen/AMDGPU/fold-freeze-fmul-to-fma.ll‎

Lines changed: 81 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -1,54 +1,98 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2-
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s -check-prefix GFX11
2+
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck %s
33

44
define float @fma_from_freeze_mul_add_left(float %x, float %y) {
5-
; GFX11-LABEL: fma_from_freeze_mul_add_left:
6-
; GFX11: ; %bb.0: ; %bb
7-
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
8-
; GFX11-NEXT: v_fma_f32 v0, v0, v1, 1.0
9-
; GFX11-NEXT: s_setpc_b64 s[30:31]
10-
bb:
11-
%mul = fmul contract float %x, %y
12-
%mul.fr = freeze float %mul
13-
%add = fadd contract float %mul.fr, 1.000000e+00
5+
; CHECK-LABEL: fma_from_freeze_mul_add_left:
6+
; CHECK: ; %bb.0:
7+
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
8+
; CHECK-NEXT: v_fma_f32 v0, v0, v1, 1.0
9+
; CHECK-NEXT: s_setpc_b64 s[30:31]
10+
%mul = fmul reassoc nsz arcp contract afn float %x, %y
11+
%mul.fr = freeze float %mul
12+
%add = fadd reassoc nsz arcp contract afn float %mul.fr, 1.000000e+00
13+
ret float %add
14+
}
15+
16+
define float @fma_from_freeze_mul_add_left_with_nnan(float %x, float %y) {
17+
; CHECK-LABEL: fma_from_freeze_mul_add_left_with_nnan:
18+
; CHECK: ; %bb.0:
19+
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
20+
; CHECK-NEXT: v_fma_f32 v0, v0, v1, 1.0
21+
; CHECK-NEXT: s_setpc_b64 s[30:31]
22+
%mul = fmul reassoc nnan nsz arcp contract afn float %x, %y
23+
%mul.fr = freeze float %mul
24+
%add = fadd reassoc nnan nsz arcp contract afn float %mul.fr, 1.000000e+00
1425
ret float %add
1526
}
1627

1728
define float @fma_from_freeze_mul_add_right(float %x, float %y) {
18-
; GFX11-LABEL: fma_from_freeze_mul_add_right:
19-
; GFX11: ; %bb.0: ; %bb
20-
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
21-
; GFX11-NEXT: v_fma_f32 v0, v0, v1, 1.0
22-
; GFX11-NEXT: s_setpc_b64 s[30:31]
23-
bb:
24-
%mul = fmul contract float %x, %y
25-
%mul.fr = freeze float %mul
26-
%add = fadd contract float 1.000000e+00, %mul.fr
29+
; CHECK-LABEL: fma_from_freeze_mul_add_right:
30+
; CHECK: ; %bb.0:
31+
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
32+
; CHECK-NEXT: v_fma_f32 v0, v0, v1, 1.0
33+
; CHECK-NEXT: s_setpc_b64 s[30:31]
34+
%mul = fmul reassoc nsz arcp contract afn float %x, %y
35+
%mul.fr = freeze float %mul
36+
%add = fadd reassoc nsz arcp contract afn float 1.000000e+00, %mul.fr
37+
ret float %add
38+
}
39+
40+
define float @fma_from_freeze_mul_add_right_with_nnan(float %x, float %y) {
41+
; CHECK-LABEL: fma_from_freeze_mul_add_right_with_nnan:
42+
; CHECK: ; %bb.0:
43+
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
44+
; CHECK-NEXT: v_fma_f32 v0, v0, v1, 1.0
45+
; CHECK-NEXT: s_setpc_b64 s[30:31]
46+
%mul = fmul reassoc nnan nsz arcp contract afn float %x, %y
47+
%mul.fr = freeze float %mul
48+
%add = fadd reassoc nnan nsz arcp contract afn float 1.000000e+00, %mul.fr
2749
ret float %add
2850
}
2951

3052
define float @fma_from_freeze_mul_sub_left(float %x, float %y) {
31-
; GFX11-LABEL: fma_from_freeze_mul_sub_left:
32-
; GFX11: ; %bb.0: ; %bb
33-
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
34-
; GFX11-NEXT: v_fma_f32 v0, v0, v1, -1.0
35-
; GFX11-NEXT: s_setpc_b64 s[30:31]
36-
bb:
37-
%mul = fmul contract float %x, %y
38-
%mul.fr = freeze float %mul
39-
%sub = fsub contract float %mul.fr, 1.000000e+00
53+
; CHECK-LABEL: fma_from_freeze_mul_sub_left:
54+
; CHECK: ; %bb.0:
55+
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
56+
; CHECK-NEXT: v_fma_f32 v0, v0, v1, -1.0
57+
; CHECK-NEXT: s_setpc_b64 s[30:31]
58+
%mul = fmul reassoc nsz arcp contract afn float %x, %y
59+
%mul.fr = freeze float %mul
60+
%sub = fsub reassoc nsz arcp contract afn float %mul.fr, 1.000000e+00
61+
ret float %sub
62+
}
63+
64+
define float @fma_from_freeze_mul_sub_left_with_nnan(float %x, float %y) {
65+
; CHECK-LABEL: fma_from_freeze_mul_sub_left_with_nnan:
66+
; CHECK: ; %bb.0:
67+
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
68+
; CHECK-NEXT: v_fma_f32 v0, v0, v1, -1.0
69+
; CHECK-NEXT: s_setpc_b64 s[30:31]
70+
%mul = fmul reassoc nnan nsz arcp contract afn float %x, %y
71+
%mul.fr = freeze float %mul
72+
%sub = fsub reassoc nnan nsz arcp contract afn float %mul.fr, 1.000000e+00
4073
ret float %sub
4174
}
4275

4376
define float @fma_from_freeze_mul_sub_right(float %x, float %y) {
44-
; GFX11-LABEL: fma_from_freeze_mul_sub_right:
45-
; GFX11: ; %bb.0: ; %bb
46-
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
47-
; GFX11-NEXT: v_fma_f32 v0, -v0, v1, 1.0
48-
; GFX11-NEXT: s_setpc_b64 s[30:31]
49-
bb:
50-
%mul = fmul contract float %x, %y
51-
%mul.fr = freeze float %mul
52-
%sub = fsub contract float 1.000000e+00, %mul.fr
77+
; CHECK-LABEL: fma_from_freeze_mul_sub_right:
78+
; CHECK: ; %bb.0:
79+
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
80+
; CHECK-NEXT: v_fma_f32 v0, -v0, v1, 1.0
81+
; CHECK-NEXT: s_setpc_b64 s[30:31]
82+
%mul = fmul reassoc nsz arcp contract afn float %x, %y
83+
%mul.fr = freeze float %mul
84+
%sub = fsub reassoc nsz arcp contract afn float 1.000000e+00, %mul.fr
85+
ret float %sub
86+
}
87+
88+
define float @fma_from_freeze_mul_sub_right_with_nnan(float %x, float %y) {
89+
; CHECK-LABEL: fma_from_freeze_mul_sub_right_with_nnan:
90+
; CHECK: ; %bb.0:
91+
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
92+
; CHECK-NEXT: v_fma_f32 v0, -v0, v1, 1.0
93+
; CHECK-NEXT: s_setpc_b64 s[30:31]
94+
%mul = fmul reassoc nnan nsz arcp contract afn float %x, %y
95+
%mul.fr = freeze float %mul
96+
%sub = fsub reassoc nnan nsz arcp contract afn float 1.000000e+00, %mul.fr
5397
ret float %sub
5498
}

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