[PowerPC] Update instruction implementation for ISA3.0+

Author: lei137

llvm/lib/Target/PowerPC/P10InstrResources.td

@@ -825,17 +825,15 @@ def : InstRW<[P10W_F2_4C, P10W_DISP_ANY, P10F2_Read, P10F2_Read, P10F2_Read],
 def : InstRW<[P10W_F2_4C, P10W_DISP_EVEN, P10W_DISP_ANY, P10F2_Read],
       (instrs
     SRADI_rec,
-    SRAWI_rec,
-    SRAWI8_rec
+    SRAWI8_rec, SRAWI_rec
 )>;
 
 // Single crack instructions
 // 4 Cycles ALU2 operations, 2 input operands
 def : InstRW<[P10W_F2_4C, P10W_DISP_EVEN, P10W_DISP_ANY, P10F2_Read, P10F2_Read],
       (instrs
     SRAD_rec,
-    SRAW_rec,
-    SRAW8_rec
+    SRAW8_rec, SRAW_rec
 )>;
 
 // 2-way crack instructions
@@ -883,7 +881,7 @@ def : InstRW<[P10W_FX_3C, P10W_DISP_ANY],
 // 3 Cycles ALU operations, 1 input operands
 def : InstRW<[P10W_FX_3C, P10W_DISP_ANY, P10FX_Read],
       (instrs
-    ADDI, ADDI8, ADDIdtprelL32, ADDItlsldLADDR32, ADDItocL, ADDItocL8, LI, LI8,
+    ADDI, ADDI8, ADDIdtprelL32, ADDItlsldLADDR32, ADDItocL, LI, LI8,
     ADDIC, ADDIC8,
     ADDIS, ADDIS8, ADDISdtprelHA32, ADDIStocHA, ADDIStocHA8, LIS, LIS8,
     ADDME, ADDME8,
@@ -1864,7 +1862,7 @@ def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_DISP_ANY, P10ST_Read, P10ST_Read]
       (instrs
     CP_PASTE8_rec, CP_PASTE_rec,
     SLBIEG,
-    TLBIE
+    TLBIE, TLBIE8P9, TLBIEP9
 )>;
 
 // Single crack instructions
@@ -1886,8 +1884,7 @@ def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_DISP_ANY, P10ST_Read, P10ST_Read,
 def : InstRW<[P10W_ST_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY],
       (instrs
     ISYNC,
-    SYNCP10,
-    SYNC
+    SYNC, SYNCP10
 )>;
 
 // Expand instructions

llvm/lib/Target/PowerPC/P9InstrResources.td

@@ -905,7 +905,7 @@ def : InstRW<[P9_LS_1C, IP_EXEC_1C, IP_AGEN_1C, DISP_3SLOTS_1C],
     SLBIEG,
     STMW,
     STSWI,
-    TLBIE
+    TLBIE, TLBIEP9, TLBIE8P9
 )>;
 
 // Vector Store Instruction

llvm/lib/Target/PowerPC/PPC.td

@@ -409,6 +409,7 @@ def HasP10Vector : Predicate<"Subtarget->hasP10Vector()">;
 def IsISA2_06 : Predicate<"Subtarget->isISA2_06()">;
 def IsISA2_07 : Predicate<"Subtarget->isISA2_07()">;
 def IsISA3_0 : Predicate<"Subtarget->isISA3_0()">;
+def IsNotISA3_0 : Predicate<"!Subtarget->isISA3_0()">;
 def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">;
 def IsNotISA3_1 : Predicate<"!Subtarget->isISA3_1()">;
 def IsISAFuture : Predicate<"Subtarget->isISAFuture()">;

llvm/lib/Target/PowerPC/PPCBack2BackFusion.def

@@ -29,7 +29,7 @@ FUSION_FEATURE(GeneralBack2Back, hasBack2BackFusion, -1,
     ADDIStocHA8,
     ADDIdtprelL32,
     ADDItlsldLADDR32,
-    ADDItocL8,
+    ADDItocL,
     ADDME,
     ADDME8,
     ADDME8O,
@@ -209,7 +209,9 @@ FUSION_FEATURE(GeneralBack2Back, hasBack2BackFusion, -1,
     SRADI,
     SRADI_32,
     SRAW,
+    SRAW8,
     SRAWI,
+    SRAWI8,
     SRD,
     SRD_rec,
     SRW,
@@ -518,7 +520,7 @@ FUSION_FEATURE(GeneralBack2Back, hasBack2BackFusion, -1,
     ADDIStocHA8,
     ADDIdtprelL32,
     ADDItlsldLADDR32,
-    ADDItocL8,
+    ADDItocL,
     ADDME,
     ADDME8,
     ADDME8O,
@@ -747,7 +749,9 @@ FUSION_FEATURE(GeneralBack2Back, hasBack2BackFusion, -1,
     SRADI,
     SRADI_32,
     SRAW,
+    SRAW8,
     SRAWI,
+    SRAWI8,
     SRD,
     SRD_rec,
     SRW,

llvm/lib/Target/PowerPC/PPCInstrFormats.td

@@ -850,6 +850,26 @@ class XForm_45<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
   let Inst{31}    = 0;
 }
 
+class XForm_RSB5_UIMM2_2UIMM1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
+                              string asmstr, list<dag> pattern>
+    : I<opcode, OOL, IOL, asmstr, NoItinerary> {
+
+  bits<5> RS;
+  bits<5> RB;
+  bits<2> RIC;
+  bits<1> PRS;
+  bits<1> R;
+
+  let Pattern = pattern;
+
+  let Inst{6...10} = RS;
+  let Inst{12...13} = RIC;
+  let Inst{14} = PRS;
+  let Inst{15} = R;
+  let Inst{16...20} = RB;
+  let Inst{21...30} = xo;
+}
+
 class X_FRT5_XO2_XO3_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, bits<10> xo,
                          dag OOL, dag IOL, string asmstr, InstrItinClass itin,
                          list<dag> pattern>

llvm/lib/Target/PowerPC/PPCInstrInfo.td

@@ -4321,7 +4321,24 @@ def TLBLI : XForm_16b<31, 1010, (outs), (ins gprc:$RB),
                           "tlbli $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
 
 def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RST, gprc:$RB),
-                          "tlbie $RB,$RST", IIC_SprTLBIE, []>;
+                     "tlbie $RB, $RST", IIC_SprTLBIE, []>,
+            Requires<[IsNotISA3_0]>;
+
+let Predicates = [IsISA3_0] in {
+  //let isCodeGenOnly = 1 in {
+    def TLBIEP9 : XForm_RSB5_UIMM2_2UIMM1<31, 306, (outs),
+                                          (ins gprc:$RB, gprc:$RS, u2imm:$RIC,
+                                              u1imm:$PRS, u1imm:$R),
+                                          "tlbie $RB, $RS, $RIC, $PRS, $R", []>;
+  //}
+  let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
+    def TLBIE8P9
+        : XForm_RSB5_UIMM2_2UIMM1<31, 306, (outs),
+                                  (ins g8rc:$RB, g8rc:$RS, u2imm:$RIC,
+                                      u1imm:$PRS, u1imm:$R),
+                                  "tlbie $RB, $RS, $RIC, $PRS, $R", []>;
+  }
+}
 
 def TLBSX : XForm_tlb<914, (outs), (ins gprc:$RA, gprc:$RB), "tlbsx $RA, $RB",
                 IIC_LdStLoad>, Requires<[IsBookE]>;
@@ -4667,7 +4684,11 @@ def : InstAlias<"mficcr $Rx", (MFSPR gprc:$Rx, 1019)>, Requires<[IsPPC4xx]>;
 
 }
 
-def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>;
+def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>,  Requires<[IsNotISA3_0]>;
+let Predicates = [IsISA3_0] in {
+  def : InstAlias<"tlbie $RB", (TLBIEP9 R0, gprc:$RB, 0, 0, 0)>;
+  def : InstAlias<"tlbie $RB, $RS", (TLBIEP9 gprc:$RB, gprc:$RS, 0, 0, 0)>;
+}
 
 def : InstAlias<"tlbrehi $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 0)>,
                 Requires<[IsPPC4xx]>;

llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-bookIII.txt

@@ -111,9 +111,6 @@
 # CHECK: tlbie 4
 0x7c 0x00 0x22 0x64
 
-# CHECK: tlbie 4
-0x7c 0x00 0x22 0x64
-
 # CHECK: rfi
 0x4c 0x00 0x00 0x64
 # CHECK: rfci

llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-p9vector.txt renamed to llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-p9.txt

@@ -2,3 +2,9 @@
 
 # CHECK: mtvsrdd 6, 0, 3
 0x66 0x1b 0xc0 0x7c
+
+# CHECK: tlbie 8, 10
+0x64, 0x42, 0x40, 0x7d
+
+# CHECK: tlbie 8, 10, 2, 1, 0
+0x64, 0x42, 0x4a, 0x7d