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Oscar Smith
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claude tries to write tests
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‎llvm/test/CodeGen/Generic/clmul-expand.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=riscv32 -mattr=-zbc,-zbkc -verify-machineinstrs | FileCheck %s --check-prefix=RV32-EXPAND
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; RUN: llc < %s -mtriple=riscv64 -mattr=-zbc,-zbkc -verify-machineinstrs | FileCheck %s --check-prefix=RV64-EXPAND
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; RUN: llc < %s -mtriple=x86_64 -verify-machineinstrs | FileCheck %s --check-prefix=X64-EXPAND
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; Test CLMUL expansion when the instruction is not natively supported
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declare i8 @llvm.clmul.i8(i8 %a, i8 %b)
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declare i16 @llvm.clmul.i16(i16 %a, i16 %b)
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declare i32 @llvm.clmul.i32(i32 %a, i32 %b)
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declare i64 @llvm.clmul.i64(i64 %a, i64 %b)
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declare i128 @llvm.clmul.i128(i128 %a, i128 %b)
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define i8 @clmul_expand_i8(i8 %a, i8 %b) nounwind {
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; RV32-EXPAND-LABEL: clmul_expand_i8:
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; RV32-EXPAND: # %bb.0:
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; RV32-EXPAND-NEXT: andi a2, a0, 1
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; RV32-EXPAND-NEXT: beqz a2, .LBB0_2
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; RV32-EXPAND-NEXT: # %bb.1:
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; RV32-EXPAND-NEXT: mv a2, a1
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; RV32-EXPAND-NEXT: j .LBB0_3
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; RV32-EXPAND-NEXT: .LBB0_2:
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; RV32-EXPAND-NEXT: li a2, 0
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; RV32-EXPAND-NEXT: .LBB0_3:
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; RV32-EXPAND-NEXT: srli a0, a0, 1
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; RV32-EXPAND-NEXT: slli a1, a1, 1
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; RV32-EXPAND-NEXT: andi a3, a0, 1
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; RV32-EXPAND-NEXT: beqz a3, .LBB0_5
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; RV32-EXPAND-NEXT: # %bb.4:
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; RV32-EXPAND-NEXT: xor a2, a2, a1
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; RV32-EXPAND-NEXT: .LBB0_5:
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; RV32-EXPAND-NEXT: srli a0, a0, 1
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; RV32-EXPAND-NEXT: slli a1, a1, 1
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; RV32-EXPAND-NEXT: andi a3, a0, 1
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; RV32-EXPAND-NEXT: beqz a3, .LBB0_7
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; RV32-EXPAND-NEXT: # %bb.6:
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; RV32-EXPAND-NEXT: xor a2, a2, a1
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; RV32-EXPAND-NEXT: .LBB0_7:
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; RV32-EXPAND-NEXT: srli a0, a0, 1
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; RV32-EXPAND-NEXT: slli a1, a1, 1
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; RV32-EXPAND-NEXT: andi a3, a0, 1
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; RV32-EXPAND-NEXT: beqz a3, .LBB0_9
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; RV32-EXPAND-NEXT: # %bb.8:
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; RV32-EXPAND-NEXT: xor a2, a2, a1
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; RV32-EXPAND-NEXT: .LBB0_9:
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; RV32-EXPAND-NEXT: srli a0, a0, 1
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; RV32-EXPAND-NEXT: slli a1, a1, 1
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; RV32-EXPAND-NEXT: andi a3, a0, 1
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; RV32-EXPAND-NEXT: beqz a3, .LBB0_11
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; RV32-EXPAND-NEXT: # %bb.10:
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; RV32-EXPAND-NEXT: xor a2, a2, a1
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; RV32-EXPAND-NEXT: .LBB0_11:
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; RV32-EXPAND-NEXT: srli a0, a0, 1
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; RV32-EXPAND-NEXT: slli a1, a1, 1
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; RV32-EXPAND-NEXT: andi a3, a0, 1
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; RV32-EXPAND-NEXT: beqz a3, .LBB0_13
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; RV32-EXPAND-NEXT: # %bb.12:
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; RV32-EXPAND-NEXT: xor a2, a2, a1
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; RV32-EXPAND-NEXT: .LBB0_13:
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; RV32-EXPAND-NEXT: srli a0, a0, 1
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; RV32-EXPAND-NEXT: slli a1, a1, 1
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; RV32-EXPAND-NEXT: andi a3, a0, 1
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; RV32-EXPAND-NEXT: beqz a3, .LBB0_15
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; RV32-EXPAND-NEXT: # %bb.14:
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; RV32-EXPAND-NEXT: xor a2, a2, a1
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; RV32-EXPAND-NEXT: .LBB0_15:
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; RV32-EXPAND-NEXT: andi a0, a0, 2
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; RV32-EXPAND-NEXT: beqz a0, .LBB0_17
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; RV32-EXPAND-NEXT: # %bb.16:
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; RV32-EXPAND-NEXT: slli a0, a1, 1
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; RV32-EXPAND-NEXT: xor a2, a2, a0
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; RV32-EXPAND-NEXT: .LBB0_17:
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; RV32-EXPAND-NEXT: mv a0, a2
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; RV32-EXPAND-NEXT: ret
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%result = call i8 @llvm.clmul.i8(i8 %a, i8 %b)
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ret i8 %result
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}
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define i16 @clmul_expand_i16(i16 %a, i16 %b) nounwind {
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; RV32-EXPAND-LABEL: clmul_expand_i16:
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; RV32-EXPAND: # %bb.0:
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; RV32-EXPAND-NEXT: andi a2, a0, 1
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; RV32-EXPAND-NEXT: beqz a2, .LBB1_2
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; RV32-EXPAND-NEXT: # %bb.1:
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; RV32-EXPAND-NEXT: mv a2, a1
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; RV32-EXPAND-NEXT: j .LBB1_3
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; RV32-EXPAND-NEXT: .LBB1_2:
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; RV32-EXPAND-NEXT: li a2, 0
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; RV32-EXPAND-NEXT: .LBB1_3:
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; RV32-EXPAND-NEXT: srli a0, a0, 1
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; RV32-EXPAND-NEXT: slli a1, a1, 1
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%result = call i16 @llvm.clmul.i16(i16 %a, i16 %b)
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ret i16 %result
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}
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define i32 @clmul_expand_i32(i32 %a, i32 %b) nounwind {
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; RV32-EXPAND-LABEL: clmul_expand_i32:
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; RV32-EXPAND: # %bb.0:
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; RV32-EXPAND-NEXT: andi a2, a0, 1
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; RV32-EXPAND-NEXT: beqz a2, .LBB2_2
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; RV32-EXPAND-NEXT: # %bb.1:
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; RV32-EXPAND-NEXT: mv a2, a1
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; RV32-EXPAND-NEXT: j .LBB2_3
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; RV32-EXPAND-NEXT: .LBB2_2:
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; RV32-EXPAND-NEXT: li a2, 0
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; RV32-EXPAND-NEXT: .LBB2_3:
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; RV32-EXPAND-NEXT: srli a0, a0, 1
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; RV32-EXPAND-NEXT: slli a1, a1, 1
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%result = call i32 @llvm.clmul.i32(i32 %a, i32 %b)
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ret i32 %result
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}
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define i64 @clmul_expand_i64(i64 %a, i64 %b) nounwind {
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; RV32-EXPAND-LABEL: clmul_expand_i64:
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; RV32-EXPAND: # %bb.0:
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; RV32-EXPAND-NEXT: addi sp, sp, -16
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; RV32-EXPAND-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32-EXPAND-NEXT: call __clmuldi3
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; RV32-EXPAND-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32-EXPAND-NEXT: addi sp, sp, 16
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; RV32-EXPAND-NEXT: ret
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;
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; RV64-EXPAND-LABEL: clmul_expand_i64:
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; RV64-EXPAND: # %bb.0:
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; RV64-EXPAND-NEXT: andi a2, a0, 1
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; RV64-EXPAND-NEXT: beqz a2, .LBB3_2
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; RV64-EXPAND-NEXT: # %bb.1:
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; RV64-EXPAND-NEXT: mv a2, a1
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; RV64-EXPAND-NEXT: j .LBB3_3
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; RV64-EXPAND-NEXT: .LBB3_2:
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; RV64-EXPAND-NEXT: li a2, 0
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; RV64-EXPAND-NEXT: .LBB3_3:
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; RV64-EXPAND-NEXT: srli a0, a0, 1
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; RV64-EXPAND-NEXT: slli a1, a1, 1
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%result = call i64 @llvm.clmul.i64(i64 %a, i64 %b)
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ret i64 %result
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}
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define i128 @clmul_expand_i128(i128 %a, i128 %b) nounwind {
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; RV32-EXPAND-LABEL: clmul_expand_i128:
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; RV32-EXPAND: # %bb.0:
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; RV32-EXPAND-NEXT: addi sp, sp, -16
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; RV32-EXPAND-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32-EXPAND-NEXT: call __clmulti3
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; RV32-EXPAND-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32-EXPAND-NEXT: addi sp, sp, 16
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; RV32-EXPAND-NEXT: ret
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;
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; RV64-EXPAND-LABEL: clmul_expand_i128:
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; RV64-EXPAND: # %bb.0:
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; RV64-EXPAND-NEXT: addi sp, sp, -16
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; RV64-EXPAND-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64-EXPAND-NEXT: call __clmulti3
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; RV64-EXPAND-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64-EXPAND-NEXT: addi sp, sp, 16
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; RV64-EXPAND-NEXT: ret
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%result = call i128 @llvm.clmul.i128(i128 %a, i128 %b)
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ret i128 %result
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}
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; Test with known constants to verify correctness
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define i8 @clmul_expand_i8_known() nounwind {
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; RV32-EXPAND-LABEL: clmul_expand_i8_known:
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; RV32-EXPAND: # %bb.0:
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; RV32-EXPAND-NEXT: li a0, 14
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; RV32-EXPAND-NEXT: ret
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;
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; RV64-EXPAND-LABEL: clmul_expand_i8_known:
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; RV64-EXPAND: # %bb.0:
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; RV64-EXPAND-NEXT: li a0, 14
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; RV64-EXPAND-NEXT: ret
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; clmul(5, 6) = clmul(0b101, 0b110) = 0b1110 = 14
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%result = call i8 @llvm.clmul.i8(i8 5, i8 6)
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ret i8 %result
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}
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define i16 @clmul_expand_i16_known() nounwind {
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; RV32-EXPAND-LABEL: clmul_expand_i16_known:
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; RV32-EXPAND: # %bb.0:
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; RV32-EXPAND-NEXT: li a0, 158
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; RV32-EXPAND-NEXT: ret
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;
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; RV64-EXPAND-LABEL: clmul_expand_i16_known:
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; RV64-EXPAND: # %bb.0:
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; RV64-EXPAND-NEXT: li a0, 158
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; RV64-EXPAND-NEXT: ret
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; clmul(15, 13) = clmul(0b1111, 0b1101) = 0b10011110 = 158
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%result = call i16 @llvm.clmul.i16(i16 15, i16 13)
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ret i16 %result
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}

‎llvm/test/CodeGen/Generic/clmul-vector.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=riscv32 -mattr=-zbc,-zbkc -verify-machineinstrs | FileCheck %s --check-prefix=RV32
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; RUN: llc < %s -mtriple=riscv64 -mattr=-zbc,-zbkc -verify-machineinstrs | FileCheck %s --check-prefix=RV64
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; RUN: llc < %s -mtriple=x86_64 -verify-machineinstrs | FileCheck %s --check-prefix=X64
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; Test CLMUL with vector types
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declare <2 x i32> @llvm.clmul.v2i32(<2 x i32> %a, <2 x i32> %b)
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declare <4 x i32> @llvm.clmul.v4i32(<4 x i32> %a, <4 x i32> %b)
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declare <2 x i64> @llvm.clmul.v2i64(<2 x i64> %a, <2 x i64> %b)
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declare <8 x i16> @llvm.clmul.v8i16(<8 x i16> %a, <8 x i16> %b)
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declare <16 x i8> @llvm.clmul.v16i8(<16 x i8> %a, <16 x i8> %b)
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define <2 x i32> @clmul_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
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; RV32-LABEL: clmul_v2i32:
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; RV32: # %bb.0:
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; RV32-NEXT: addi sp, sp, -32
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; RV32-NEXT: sw s0, 28(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s1, 24(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s2, 20(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s3, 16(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s4, 12(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s5, 8(sp) # 4-byte Folded Spill
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; RV32-NEXT: mv s0, a3
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; RV32-NEXT: mv s1, a2
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; RV32-NEXT: mv s2, a1
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; RV32-NEXT: mv s3, a0
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; RV32-NEXT: andi a0, a3, 1
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; RV32-NEXT: beqz a0, .LBB0_2
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; RV32-NEXT: # %bb.1:
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; RV32-NEXT: mv s4, s1
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; RV32-NEXT: j .LBB0_3
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; RV32-NEXT: .LBB0_2:
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; RV32-NEXT: li s4, 0
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; RV32-NEXT: .LBB0_3:
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; RV32-NEXT: srli s0, s0, 1
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; RV32-NEXT: slli s1, s1, 1
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%result = call <2 x i32> @llvm.clmul.v2i32(<2 x i32> %a, <2 x i32> %b)
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ret <2 x i32> %result
40+
}
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define <4 x i32> @clmul_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
43+
; RV32-LABEL: clmul_v4i32:
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; RV32: # %bb.0:
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; RV32-NEXT: addi sp, sp, -80
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; RV32-NEXT: sw ra, 76(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s0, 72(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s1, 68(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s2, 64(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s3, 60(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s4, 56(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s5, 52(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s6, 48(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s7, 44(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s8, 40(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s9, 36(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s10, 32(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s11, 28(sp) # 4-byte Folded Spill
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%result = call <4 x i32> @llvm.clmul.v4i32(<4 x i32> %a, <4 x i32> %b)
60+
ret <4 x i32> %result
61+
}
62+
63+
define <2 x i64> @clmul_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
64+
; RV32-LABEL: clmul_v2i64:
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; RV32: # %bb.0:
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; RV32-NEXT: addi sp, sp, -48
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; RV32-NEXT: sw ra, 44(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s0, 40(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s1, 36(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s2, 32(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s3, 28(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s4, 24(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s5, 20(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s6, 16(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s7, 12(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s8, 8(sp) # 4-byte Folded Spill
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; RV32-NEXT: lw s0, 64(sp)
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; RV32-NEXT: lw s1, 68(sp)
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; RV32-NEXT: lw s2, 72(sp)
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; RV32-NEXT: lw s3, 76(sp)
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; RV32-NEXT: mv s4, a0
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; RV32-NEXT: mv s5, a1
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; RV32-NEXT: mv s6, a2
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; RV32-NEXT: mv s7, a3
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; RV32-NEXT: mv a0, s6
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; RV32-NEXT: mv a1, s7
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; RV32-NEXT: mv a2, s2
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; RV32-NEXT: mv a3, s3
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; RV32-NEXT: call __clmuldi3
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; RV32-NEXT: mv s8, a0
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; RV32-NEXT: mv s2, a1
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; RV32-NEXT: mv a0, s4
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; RV32-NEXT: mv a1, s5
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; RV32-NEXT: mv a2, s0
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; RV32-NEXT: mv a3, s1
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; RV32-NEXT: call __clmuldi3
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; RV32-NEXT: mv a2, a0
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; RV32-NEXT: mv a3, a1
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; RV32-NEXT: mv a0, a2
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; RV32-NEXT: mv a1, a3
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; RV32-NEXT: mv a2, s8
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; RV32-NEXT: mv a3, s2
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; RV32-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
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; RV32-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
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; RV32-NEXT: lw s1, 36(sp) # 4-byte Folded Reload
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; RV32-NEXT: lw s2, 32(sp) # 4-byte Folded Reload
107+
; RV32-NEXT: lw s3, 28(sp) # 4-byte Folded Reload
108+
; RV32-NEXT: lw s4, 24(sp) # 4-byte Folded Reload
109+
; RV32-NEXT: lw s5, 20(sp) # 4-byte Folded Reload
110+
; RV32-NEXT: lw s6, 16(sp) # 4-byte Folded Reload
111+
; RV32-NEXT: lw s7, 12(sp) # 4-byte Folded Reload
112+
; RV32-NEXT: lw s8, 8(sp) # 4-byte Folded Reload
113+
; RV32-NEXT: addi sp, sp, 48
114+
; RV32-NEXT: ret
115+
%result = call <2 x i64> @llvm.clmul.v2i64(<2 x i64> %a, <2 x i64> %b)
116+
ret <2 x i64> %result
117+
}
118+
119+
define <8 x i16> @clmul_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind {
120+
; RV32-LABEL: clmul_v8i16:
121+
; RV32: # %bb.0:
122+
; RV32-NEXT: addi sp, sp, -144
123+
; RV32-NEXT: sw ra, 140(sp) # 4-byte Folded Spill
124+
; RV32-NEXT: sw s0, 136(sp) # 4-byte Folded Spill
125+
%result = call <8 x i16> @llvm.clmul.v8i16(<8 x i16> %a, <8 x i16> %b)
126+
ret <8 x i16> %result
127+
}
128+
129+
define <16 x i8> @clmul_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
130+
; RV32-LABEL: clmul_v16i8:
131+
; RV32: # %bb.0:
132+
; RV32-NEXT: addi sp, sp, -272
133+
; RV32-NEXT: sw ra, 268(sp) # 4-byte Folded Spill
134+
; RV32-NEXT: sw s0, 264(sp) # 4-byte Folded Spill
135+
%result = call <16 x i8> @llvm.clmul.v16i8(<16 x i8> %a, <16 x i8> %b)
136+
ret <16 x i8> %result
137+
}
138+
139+
; Test with splat vectors
140+
define <2 x i32> @clmul_v2i32_splat(<2 x i32> %a) nounwind {
141+
; RV32-LABEL: clmul_v2i32_splat:
142+
; RV32: # %bb.0:
143+
; RV32-NEXT: addi sp, sp, -32
144+
; RV32-NEXT: sw s0, 28(sp) # 4-byte Folded Spill
145+
; RV32-NEXT: sw s1, 24(sp) # 4-byte Folded Spill
146+
; RV32-NEXT: sw s2, 20(sp) # 4-byte Folded Spill
147+
; RV32-NEXT: sw s3, 16(sp) # 4-byte Folded Spill
148+
; RV32-NEXT: sw s4, 12(sp) # 4-byte Folded Spill
149+
; RV32-NEXT: sw s5, 8(sp) # 4-byte Folded Spill
150+
; RV32-NEXT: mv s0, a1
151+
; RV32-NEXT: mv s1, a0
152+
; RV32-NEXT: andi a0, a1, 1
153+
; RV32-NEXT: li s2, 3
154+
; RV32-NEXT: beqz a0, .LBB5_2
155+
; RV32-NEXT: # %bb.1:
156+
; RV32-NEXT: mv s3, s2
157+
; RV32-NEXT: j .LBB5_3
158+
; RV32-NEXT: .LBB5_2:
159+
; RV32-NEXT: li s3, 0
160+
; RV32-NEXT: .LBB5_3:
161+
; RV32-NEXT: srli s0, s0, 1
162+
; RV32-NEXT: slli s2, s2, 1
163+
%splat = insertelement <2 x i32> poison, i32 3, i32 0
164+
%splat_vec = shufflevector <2 x i32> %splat, <2 x i32> poison, <2 x i32> zeroinitializer
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%result = call <2 x i32> @llvm.clmul.v2i32(<2 x i32> %a, <2 x i32> %splat_vec)
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ret <2 x i32> %result
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}
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; Test with constant vectors
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define <2 x i32> @clmul_v2i32_const() nounwind {
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; RV32-LABEL: clmul_v2i32_const:
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; RV32: # %bb.0:
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; RV32-NEXT: li a0, 14
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; RV32-NEXT: li a1, 6
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; RV32-NEXT: ret
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%result = call <2 x i32> @llvm.clmul.v2i32(<2 x i32> <i32 5, i32 2>, <2 x i32> <i32 6, i32 3>)
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ret <2 x i32> %result
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}

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