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[flang][OMPIRBuilder][MLIR][llvm] Backend support for atomic control options (#151579)
Adding mlir to llvm support for atomic control options. Atomic Control Options are used to specify architectural characteristics to help lowering of atomic operations. The options used are: `-f[no-]atomic-remote-memory`, `-f[no-]atomic-fine-grained-memory`, `-f[no-]atomic-ignore-denormal-mode`. Legacy option `-m[no-]unsafe-fp-atomics` is aliased to `-f[no-]ignore-denormal-mode`. More details can be found in #102569. This PR implements the MLIR to LLVM lowering support of atomic control attributes specified with OpenMP `atomicUpdateOp`. Initial support can be found in PR: #150860
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‎flang/test/Driver/atomic-control-options.f90‎

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,20 @@
1+
! REQUIRES: amdgpu-registered-target
2+
! RUN: %flang_fc1 -emit-llvm -triple amdgcn-amd-amdhsa -fopenmp -fopenmp-is-device -munsafe-fp-atomics %s -o -|FileCheck -check-prefix=UNSAFE-FP-ATOMICS %s
3+
! RUN: %flang_fc1 -emit-llvm -triple amdgcn-amd-amdhsa -fopenmp -fopenmp-is-device -fatomic-ignore-denormal-mode %s -o -|FileCheck -check-prefix=IGNORE-DENORMAL-MODE %s
4+
! RUN: %flang_fc1 -emit-llvm -triple amdgcn-amd-amdhsa -fopenmp -fopenmp-is-device -fatomic-fine-grained-memory %s -o -|FileCheck -check-prefix=FINE-GRAINED-MEMORY %s
5+
! RUN: %flang_fc1 -emit-llvm -triple amdgcn-amd-amdhsa -fopenmp -fopenmp-is-device -fatomic-remote-memory %s -o -|FileCheck -check-prefix=REMOTE-MEMORY %s
6+
program test
7+
implicit none
8+
integer :: A, threads
9+
threads = 128
10+
A = 0
11+
!$omp target parallel num_threads(threads)
12+
!$omp atomic
13+
A = A + 1
14+
!$omp end target parallel
15+
end program test
16+
17+
!UNSAFE-FP-ATOMICS: %{{.*}} = atomicrmw add ptr {{.*}}, i32 1 monotonic, align 4, !amdgpu.ignore.denormal.mode !{{.*}}, !amdgpu.no.fine.grained.memory !{{.*}}, !amdgpu.no.remote.memory !{{.*}}
18+
!IGNORE-DENORMAL-MODE: %{{.*}} = atomicrmw add ptr {{.*}}, i32 1 monotonic, align 4, !amdgpu.ignore.denormal.mode !{{.*}}, !amdgpu.no.fine.grained.memory !{{.*}}, !amdgpu.no.remote.memory !{{.*}}
19+
!FINE-GRAINED-MEMORY: %{{.*}} = atomicrmw add ptr {{.*}}, i32 1 monotonic, align 4, !amdgpu.no.remote.memory !{{.*}}
20+
!REMOTE-MEMORY: %{{.*}} = atomicrmw add ptr {{.*}}, i32 1 monotonic, align 4, !amdgpu.no.fine.grained.memory !{{.*}}

‎llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h‎

Lines changed: 8 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3286,7 +3286,8 @@ class OpenMPIRBuilder {
32863286
emitAtomicUpdate(InsertPointTy AllocaIP, Value *X, Type *XElemTy, Value *Expr,
32873287
AtomicOrdering AO, AtomicRMWInst::BinOp RMWOp,
32883288
AtomicUpdateCallbackTy &UpdateOp, bool VolatileX,
3289-
bool IsXBinopExpr);
3289+
bool IsXBinopExpr, bool IsIgnoreDenormalMode,
3290+
bool IsFineGrainedMemory, bool IsRemoteMemory);
32903291

32913292
/// Emit the binary op. described by \p RMWOp, using \p Src1 and \p Src2 .
32923293
///
@@ -3359,7 +3360,9 @@ class OpenMPIRBuilder {
33593360
LLVM_ABI InsertPointOrErrorTy createAtomicUpdate(
33603361
const LocationDescription &Loc, InsertPointTy AllocaIP, AtomicOpValue &X,
33613362
Value *Expr, AtomicOrdering AO, AtomicRMWInst::BinOp RMWOp,
3362-
AtomicUpdateCallbackTy &UpdateOp, bool IsXBinopExpr);
3363+
AtomicUpdateCallbackTy &UpdateOp, bool IsXBinopExpr,
3364+
bool IsIgnoreDenormalMode = false, bool IsFineGrainedMemory = false,
3365+
bool IsRemoteMemory = false);
33633366

33643367
/// Emit atomic update for constructs: --- Only Scalar data types
33653368
/// V = X; X = X BinOp Expr ,
@@ -3394,7 +3397,9 @@ class OpenMPIRBuilder {
33943397
const LocationDescription &Loc, InsertPointTy AllocaIP, AtomicOpValue &X,
33953398
AtomicOpValue &V, Value *Expr, AtomicOrdering AO,
33963399
AtomicRMWInst::BinOp RMWOp, AtomicUpdateCallbackTy &UpdateOp,
3397-
bool UpdateExpr, bool IsPostfixUpdate, bool IsXBinopExpr);
3400+
bool UpdateExpr, bool IsPostfixUpdate, bool IsXBinopExpr,
3401+
bool IsIgnoreDenormalMode = false, bool IsFineGrainedMemory = false,
3402+
bool IsRemoteMemory = false);
33983403

33993404
/// Emit atomic compare for constructs: --- Only scalar data types
34003405
/// cond-expr-stmt:

‎llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp‎

Lines changed: 26 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -8956,7 +8956,8 @@ OpenMPIRBuilder::createAtomicWrite(const LocationDescription &Loc,
89568956
OpenMPIRBuilder::InsertPointOrErrorTy OpenMPIRBuilder::createAtomicUpdate(
89578957
const LocationDescription &Loc, InsertPointTy AllocaIP, AtomicOpValue &X,
89588958
Value *Expr, AtomicOrdering AO, AtomicRMWInst::BinOp RMWOp,
8959-
AtomicUpdateCallbackTy &UpdateOp, bool IsXBinopExpr) {
8959+
AtomicUpdateCallbackTy &UpdateOp, bool IsXBinopExpr,
8960+
bool IsIgnoreDenormalMode, bool IsFineGrainedMemory, bool IsRemoteMemory) {
89608961
assert(!isConflictIP(Loc.IP, AllocaIP) && "IPs must not be ambiguous");
89618962
if (!updateToLocation(Loc))
89628963
return Loc.IP;
@@ -8974,9 +8975,9 @@ OpenMPIRBuilder::InsertPointOrErrorTy OpenMPIRBuilder::createAtomicUpdate(
89748975
"OpenMP atomic does not support LT or GT operations");
89758976
});
89768977

8977-
Expected<std::pair<Value *, Value *>> AtomicResult =
8978-
emitAtomicUpdate(AllocaIP, X.Var, X.ElemTy, Expr, AO, RMWOp, UpdateOp,
8979-
X.IsVolatile, IsXBinopExpr);
8978+
Expected<std::pair<Value *, Value *>> AtomicResult = emitAtomicUpdate(
8979+
AllocaIP, X.Var, X.ElemTy, Expr, AO, RMWOp, UpdateOp, X.IsVolatile,
8980+
IsXBinopExpr, IsIgnoreDenormalMode, IsFineGrainedMemory, IsRemoteMemory);
89808981
if (!AtomicResult)
89818982
return AtomicResult.takeError();
89828983
checkAndEmitFlushAfterAtomic(Loc, AO, AtomicKind::Update);
@@ -9023,7 +9024,8 @@ Value *OpenMPIRBuilder::emitRMWOpAsInstruction(Value *Src1, Value *Src2,
90239024
Expected<std::pair<Value *, Value *>> OpenMPIRBuilder::emitAtomicUpdate(
90249025
InsertPointTy AllocaIP, Value *X, Type *XElemTy, Value *Expr,
90259026
AtomicOrdering AO, AtomicRMWInst::BinOp RMWOp,
9026-
AtomicUpdateCallbackTy &UpdateOp, bool VolatileX, bool IsXBinopExpr) {
9027+
AtomicUpdateCallbackTy &UpdateOp, bool VolatileX, bool IsXBinopExpr,
9028+
bool IsIgnoreDenormalMode, bool IsFineGrainedMemory, bool IsRemoteMemory) {
90279029
// TODO: handle the case where XElemTy is not byte-sized or not a power of 2
90289030
// or a complex datatype.
90299031
bool emitRMWOp = false;
@@ -9046,7 +9048,20 @@ Expected<std::pair<Value *, Value *>> OpenMPIRBuilder::emitAtomicUpdate(
90469048

90479049
std::pair<Value *, Value *> Res;
90489050
if (emitRMWOp) {
9049-
Res.first = Builder.CreateAtomicRMW(RMWOp, X, Expr, llvm::MaybeAlign(), AO);
9051+
AtomicRMWInst *RMWInst =
9052+
Builder.CreateAtomicRMW(RMWOp, X, Expr, llvm::MaybeAlign(), AO);
9053+
if (T.isAMDGPU()) {
9054+
if (IsIgnoreDenormalMode)
9055+
RMWInst->setMetadata("amdgpu.ignore.denormal.mode",
9056+
llvm::MDNode::get(Builder.getContext(), {}));
9057+
if (!IsFineGrainedMemory)
9058+
RMWInst->setMetadata("amdgpu.no.fine.grained.memory",
9059+
llvm::MDNode::get(Builder.getContext(), {}));
9060+
if (!IsRemoteMemory)
9061+
RMWInst->setMetadata("amdgpu.no.remote.memory",
9062+
llvm::MDNode::get(Builder.getContext(), {}));
9063+
}
9064+
Res.first = RMWInst;
90509065
// not needed except in case of postfix captures. Generate anyway for
90519066
// consistency with the else part. Will be removed with any DCE pass.
90529067
// AtomicRMWInst::Xchg does not have a coressponding instruction.
@@ -9178,7 +9193,8 @@ OpenMPIRBuilder::InsertPointOrErrorTy OpenMPIRBuilder::createAtomicCapture(
91789193
const LocationDescription &Loc, InsertPointTy AllocaIP, AtomicOpValue &X,
91799194
AtomicOpValue &V, Value *Expr, AtomicOrdering AO,
91809195
AtomicRMWInst::BinOp RMWOp, AtomicUpdateCallbackTy &UpdateOp,
9181-
bool UpdateExpr, bool IsPostfixUpdate, bool IsXBinopExpr) {
9196+
bool UpdateExpr, bool IsPostfixUpdate, bool IsXBinopExpr,
9197+
bool IsIgnoreDenormalMode, bool IsFineGrainedMemory, bool IsRemoteMemory) {
91829198
if (!updateToLocation(Loc))
91839199
return Loc.IP;
91849200

@@ -9197,9 +9213,9 @@ OpenMPIRBuilder::InsertPointOrErrorTy OpenMPIRBuilder::createAtomicCapture(
91979213
// If UpdateExpr is 'x' updated with some `expr` not based on 'x',
91989214
// 'x' is simply atomically rewritten with 'expr'.
91999215
AtomicRMWInst::BinOp AtomicOp = (UpdateExpr ? RMWOp : AtomicRMWInst::Xchg);
9200-
Expected<std::pair<Value *, Value *>> AtomicResult =
9201-
emitAtomicUpdate(AllocaIP, X.Var, X.ElemTy, Expr, AO, AtomicOp, UpdateOp,
9202-
X.IsVolatile, IsXBinopExpr);
9216+
Expected<std::pair<Value *, Value *>> AtomicResult = emitAtomicUpdate(
9217+
AllocaIP, X.Var, X.ElemTy, Expr, AO, AtomicOp, UpdateOp, X.IsVolatile,
9218+
IsXBinopExpr, IsIgnoreDenormalMode, IsFineGrainedMemory, IsRemoteMemory);
92039219
if (!AtomicResult)
92049220
return AtomicResult.takeError();
92059221
Value *CapturedVal =

‎mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp‎

Lines changed: 31 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3205,6 +3205,23 @@ llvm::AtomicRMWInst::BinOp convertBinOpToAtomic(Operation &op) {
32053205
.Default(llvm::AtomicRMWInst::BinOp::BAD_BINOP);
32063206
}
32073207

3208+
void extractAtomicControlFlags(omp::AtomicUpdateOp atomicUpdateOp,
3209+
bool &isIgnoreDenormalMode,
3210+
bool &isFineGrainedMemory,
3211+
bool &isRemoteMemory) {
3212+
isIgnoreDenormalMode = false;
3213+
isFineGrainedMemory = false;
3214+
isRemoteMemory = false;
3215+
if (atomicUpdateOp &&
3216+
atomicUpdateOp->hasAttr(atomicUpdateOp.getAtomicControlAttrName())) {
3217+
mlir::omp::AtomicControlAttr atomicControlAttr =
3218+
atomicUpdateOp.getAtomicControlAttr();
3219+
isIgnoreDenormalMode = atomicControlAttr.getIgnoreDenormalMode();
3220+
isFineGrainedMemory = atomicControlAttr.getFineGrainedMemory();
3221+
isRemoteMemory = atomicControlAttr.getRemoteMemory();
3222+
}
3223+
}
3224+
32083225
/// Converts an OpenMP atomic update operation using OpenMPIRBuilder.
32093226
static LogicalResult
32103227
convertOmpAtomicUpdate(omp::AtomicUpdateOp &opInst,
@@ -3269,13 +3286,19 @@ convertOmpAtomicUpdate(omp::AtomicUpdateOp &opInst,
32693286
return moduleTranslation.lookupValue(yieldop.getResults()[0]);
32703287
};
32713288

3289+
bool isIgnoreDenormalMode;
3290+
bool isFineGrainedMemory;
3291+
bool isRemoteMemory;
3292+
extractAtomicControlFlags(opInst, isIgnoreDenormalMode, isFineGrainedMemory,
3293+
isRemoteMemory);
32723294
// Handle ambiguous alloca, if any.
32733295
auto allocaIP = findAllocaInsertPoint(builder, moduleTranslation);
32743296
llvm::OpenMPIRBuilder::LocationDescription ompLoc(builder);
32753297
llvm::OpenMPIRBuilder::InsertPointOrErrorTy afterIP =
32763298
ompBuilder->createAtomicUpdate(ompLoc, allocaIP, llvmAtomicX, llvmExpr,
32773299
atomicOrdering, binop, updateFn,
3278-
isXBinopExpr);
3300+
isXBinopExpr, isIgnoreDenormalMode,
3301+
isFineGrainedMemory, isRemoteMemory);
32793302

32803303
if (failed(handleError(afterIP, *opInst)))
32813304
return failure();
@@ -3364,13 +3387,19 @@ convertOmpAtomicCapture(omp::AtomicCaptureOp atomicCaptureOp,
33643387
return moduleTranslation.lookupValue(yieldop.getResults()[0]);
33653388
};
33663389

3390+
bool isIgnoreDenormalMode;
3391+
bool isFineGrainedMemory;
3392+
bool isRemoteMemory;
3393+
extractAtomicControlFlags(atomicUpdateOp, isIgnoreDenormalMode,
3394+
isFineGrainedMemory, isRemoteMemory);
33673395
// Handle ambiguous alloca, if any.
33683396
auto allocaIP = findAllocaInsertPoint(builder, moduleTranslation);
33693397
llvm::OpenMPIRBuilder::LocationDescription ompLoc(builder);
33703398
llvm::OpenMPIRBuilder::InsertPointOrErrorTy afterIP =
33713399
ompBuilder->createAtomicCapture(
33723400
ompLoc, allocaIP, llvmAtomicX, llvmAtomicV, llvmExpr, atomicOrdering,
3373-
binop, updateFn, atomicUpdateOp, isPostfixUpdate, isXBinopExpr);
3401+
binop, updateFn, atomicUpdateOp, isPostfixUpdate, isXBinopExpr,
3402+
isIgnoreDenormalMode, isFineGrainedMemory, isRemoteMemory);
33743403

33753404
if (failed(handleError(afterIP, *atomicCaptureOp)))
33763405
return failure();

‎mlir/test/Target/LLVMIR/omptarget-atomic-capture-control-options.mlir‎

Lines changed: 44 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,44 @@
1+
// RUN: mlir-translate -mlir-to-llvmir %s | FileCheck %s
2+
3+
// CHECK: atomicrmw add ptr %loadgep_, i32 1 monotonic, align 4, !amdgpu.no.remote.memory !{{.*}}
4+
5+
module attributes {dlti.dl_spec = #dlti.dl_spec<!llvm.ptr = dense<64> : vector<4xi64>, !llvm.ptr<1> = dense<64> : vector<4xi64>, !llvm.ptr<2> = dense<32> : vector<4xi64>, !llvm.ptr<3> = dense<32> : vector<4xi64>, !llvm.ptr<4> = dense<64> : vector<4xi64>, !llvm.ptr<5> = dense<32> : vector<4xi64>, !llvm.ptr<6> = dense<32> : vector<4xi64>, !llvm.ptr<7> = dense<[160, 256, 256, 32]> : vector<4xi64>, !llvm.ptr<8> = dense<[128, 128, 128, 48]> : vector<4xi64>, !llvm.ptr<9> = dense<[192, 256, 256, 32]> : vector<4xi64>, i64 = dense<64> : vector<2xi64>, i1 = dense<8> : vector<2xi64>, i8 = dense<8> : vector<2xi64>, i16 = dense<16> : vector<2xi64>, i32 = dense<32> : vector<2xi64>, f16 = dense<16> : vector<2xi64>, f64 = dense<64> : vector<2xi64>, f128 = dense<128> : vector<2xi64>, "dlti.endianness" = "little", "dlti.legal_int_widths" = array<i32: 32, 64>, "dlti.stack_alignment" = 32 : i64, "dlti.alloca_memory_space" = 5 : ui64, "dlti.global_memory_space" = 1 : ui64>, fir.atomic_fine_grained_memory, fir.defaultkind = "a1c4d8i4l4r4", fir.kindmap = "", fir.target_cpu = "generic-hsa", llvm.data_layout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9", llvm.target_triple = "amdgcn-amd-amdhsa", omp.flags = #omp.flags<openmp_device_version = 31>, omp.is_gpu = true, omp.is_target_device = true, omp.requires = #omp<clause_requires none>, omp.target_triples = [], omp.version = #omp.version<version = 31>} {
6+
llvm.func @_QQmain() attributes {fir.bindc_name = "TEST", omp.declare_target = #omp.declaretarget<device_type = (host), capture_clause = (to)>, target_cpu = "generic-hsa"} {
7+
%0 = llvm.mlir.constant(1 : i64) : i64
8+
%1 = llvm.alloca %0 x i32 {bindc_name = "threads"} : (i64) -> !llvm.ptr<5>
9+
%2 = llvm.addrspacecast %1 : !llvm.ptr<5> to !llvm.ptr
10+
%3 = llvm.mlir.constant(1 : i64) : i64
11+
%4 = llvm.alloca %3 x i32 {bindc_name = "capture"} : (i64) -> !llvm.ptr<5>
12+
%5 = llvm.addrspacecast %4 : !llvm.ptr<5> to !llvm.ptr
13+
%6 = llvm.mlir.constant(1 : i64) : i64
14+
%7 = llvm.alloca %6 x i32 {bindc_name = "a"} : (i64) -> !llvm.ptr<5>
15+
%8 = llvm.addrspacecast %7 : !llvm.ptr<5> to !llvm.ptr
16+
%9 = llvm.mlir.constant(0 : i32) : i32
17+
%10 = llvm.mlir.constant(128 : i32) : i32
18+
%11 = llvm.mlir.constant(1 : i64) : i64
19+
%12 = llvm.mlir.constant(1 : i64) : i64
20+
%13 = llvm.mlir.constant(1 : i64) : i64
21+
llvm.store %10, %2 : i32, !llvm.ptr
22+
llvm.store %9, %8 : i32, !llvm.ptr
23+
%14 = omp.map.info var_ptr(%2 : !llvm.ptr, i32) map_clauses(implicit, exit_release_or_enter_alloc) capture(ByCopy) -> !llvm.ptr {name = "threads"}
24+
%15 = omp.map.info var_ptr(%5 : !llvm.ptr, i32) map_clauses(implicit, exit_release_or_enter_alloc) capture(ByCopy) -> !llvm.ptr {name = "capture"}
25+
%16 = omp.map.info var_ptr(%8 : !llvm.ptr, i32) map_clauses(implicit, exit_release_or_enter_alloc) capture(ByCopy) -> !llvm.ptr {name = "a"}
26+
omp.target map_entries(%14 -> %arg0, %15 -> %arg1, %16 -> %arg2 : !llvm.ptr, !llvm.ptr, !llvm.ptr) {
27+
%17 = llvm.mlir.constant(1 : i32) : i32
28+
%18 = llvm.load %arg0 : !llvm.ptr -> i32
29+
omp.parallel num_threads(%18 : i32) {
30+
omp.atomic.capture {
31+
omp.atomic.read %arg1 = %arg2 : !llvm.ptr, !llvm.ptr, i32
32+
omp.atomic.update %arg2 : !llvm.ptr {
33+
^bb0(%arg3: i32):
34+
%19 = llvm.add %arg3, %17 : i32
35+
omp.yield(%19 : i32)
36+
} {atomic_control = #omp.atomic_control<fine_grained_memory = true>}
37+
}
38+
omp.terminator
39+
}
40+
omp.terminator
41+
}
42+
llvm.return
43+
}
44+
}

‎mlir/test/Target/LLVMIR/omptarget-atomic-update-control-options.mlir‎

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,36 @@
1+
// RUN: mlir-translate -mlir-to-llvmir %s | FileCheck %s
2+
3+
// CHECK: atomicrmw add ptr %loadgep_, i32 1 monotonic, align 4, !amdgpu.ignore.denormal.mode !{{.*}}, !amdgpu.no.fine.grained.memory !{{.*}}, !amdgpu.no.remote.memory !{{.*}}
4+
5+
module attributes {dlti.dl_spec = #dlti.dl_spec<!llvm.ptr = dense<64> : vector<4xi64>, !llvm.ptr<1> = dense<64> : vector<4xi64>, !llvm.ptr<2> = dense<32> : vector<4xi64>, !llvm.ptr<3> = dense<32> : vector<4xi64>, !llvm.ptr<4> = dense<64> : vector<4xi64>, !llvm.ptr<5> = dense<32> : vector<4xi64>, !llvm.ptr<6> = dense<32> : vector<4xi64>, !llvm.ptr<7> = dense<[160, 256, 256, 32]> : vector<4xi64>, !llvm.ptr<8> = dense<[128, 128, 128, 48]> : vector<4xi64>, !llvm.ptr<9> = dense<[192, 256, 256, 32]> : vector<4xi64>, i64 = dense<64> : vector<2xi64>, i1 = dense<8> : vector<2xi64>, i8 = dense<8> : vector<2xi64>, i16 = dense<16> : vector<2xi64>, i32 = dense<32> : vector<2xi64>, f16 = dense<16> : vector<2xi64>, f64 = dense<64> : vector<2xi64>, f128 = dense<128> : vector<2xi64>, "dlti.endianness" = "little", "dlti.legal_int_widths" = array<i32: 32, 64>, "dlti.stack_alignment" = 32 : i64, "dlti.alloca_memory_space" = 5 : ui64, "dlti.global_memory_space" = 1 : ui64>, fir.atomic_ignore_denormal_mode, fir.defaultkind = "a1c4d8i4l4r4", fir.kindmap = "", fir.target_cpu = "generic-hsa", llvm.data_layout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9", llvm.target_triple = "amdgcn-amd-amdhsa", omp.flags = #omp.flags<openmp_device_version = 31>, omp.is_gpu = true, omp.is_target_device = true, omp.requires = #omp<clause_requires none>, omp.target_triples = [], omp.version = #omp.version<version = 31>} {
6+
llvm.func @_QQmain() attributes {fir.bindc_name = "TEST", omp.declare_target = #omp.declaretarget<device_type = (host), capture_clause = (to)>, target_cpu = "generic-hsa"} {
7+
%0 = llvm.mlir.constant(1 : i64) : i64
8+
%1 = llvm.alloca %0 x i32 {bindc_name = "threads"} : (i64) -> !llvm.ptr<5>
9+
%2 = llvm.addrspacecast %1 : !llvm.ptr<5> to !llvm.ptr
10+
%3 = llvm.mlir.constant(1 : i64) : i64
11+
%4 = llvm.alloca %3 x i32 {bindc_name = "a"} : (i64) -> !llvm.ptr<5>
12+
%5 = llvm.addrspacecast %4 : !llvm.ptr<5> to !llvm.ptr
13+
%6 = llvm.mlir.constant(0 : i32) : i32
14+
%7 = llvm.mlir.constant(128 : i32) : i32
15+
%8 = llvm.mlir.constant(1 : i64) : i64
16+
%9 = llvm.mlir.constant(1 : i64) : i64
17+
llvm.store %7, %2 : i32, !llvm.ptr
18+
llvm.store %6, %5 : i32, !llvm.ptr
19+
%10 = omp.map.info var_ptr(%2 : !llvm.ptr, i32) map_clauses(implicit, exit_release_or_enter_alloc) capture(ByCopy) -> !llvm.ptr {name = "threads"}
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%11 = omp.map.info var_ptr(%5 : !llvm.ptr, i32) map_clauses(implicit, exit_release_or_enter_alloc) capture(ByCopy) -> !llvm.ptr {name = "a"}
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omp.target map_entries(%10 -> %arg0, %11 -> %arg1 : !llvm.ptr, !llvm.ptr) {
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%12 = llvm.mlir.constant(1 : i32) : i32
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%13 = llvm.load %arg0 : !llvm.ptr -> i32
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omp.parallel num_threads(%13 : i32) {
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omp.atomic.update %arg1 : !llvm.ptr {
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^bb0(%arg2: i32):
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%14 = llvm.add %arg2, %12 : i32
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omp.yield(%14 : i32)
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} {atomic_control = #omp.atomic_control<ignore_denormal_mode = true>}
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omp.terminator
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}
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omp.terminator
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}
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llvm.return
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}
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}

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