Further work

Author: mtsokol

llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

@@ -382,8 +382,14 @@ class LegalizationArtifactCombiner {
     assert(Opcode == TargetOpcode::G_ANYEXT || Opcode == TargetOpcode::G_ZEXT ||
            Opcode == TargetOpcode::G_SEXT);
 
-    if (MachineInstr *DefMI = getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF,
-                                           MI.getOperand(1).getReg(), MRI)) {
+    // FIXME: Two opcodes should be checked with one call instead.
+    MachineInstr *DefMI = getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF,
+                                       MI.getOperand(1).getReg(), MRI);
+    if (!DefMI) {
+      DefMI =
+          getOpcodeDef(TargetOpcode::G_POISON, MI.getOperand(1).getReg(), MRI);
+    }
+    if (DefMI) {
       Builder.setInstr(MI);
       Register DstReg = MI.getOperand(0).getReg();
       LLT DstTy = MRI.getType(DstReg);
@@ -392,6 +398,8 @@ class LegalizationArtifactCombiner {
         // G_ANYEXT (G_IMPLICIT_DEF) -> G_IMPLICIT_DEF
         if (!isInstLegal({TargetOpcode::G_IMPLICIT_DEF, {DstTy}}))
           return false;
+        if (!isInstLegal({TargetOpcode::G_POISON, {DstTy}}))
+          return false;
         LLVM_DEBUG(dbgs() << ".. Combine G_ANYEXT(G_IMPLICIT_DEF): " << MI);
         auto Impl = Builder.buildUndef(DstTy);
         replaceRegOrBuildCopy(DstReg, Impl.getReg(0), MRI, Builder, UpdatedDefs,
@@ -951,8 +959,10 @@ class LegalizationArtifactCombiner {
           if (i - MergeStartIdx != EltUnmergeIdx - UnmergeIdxStart)
             return false;
         } else if (!AllowUndef ||
-                   MRI.getVRegDef(MI.getSourceReg(i))->getOpcode() !=
-                       TargetOpcode::G_IMPLICIT_DEF)
+                   (MRI.getVRegDef(MI.getSourceReg(i))->getOpcode() !=
+                        TargetOpcode::G_IMPLICIT_DEF &&
+                    MRI.getVRegDef(MI.getSourceReg(i))->getOpcode() !=
+                        TargetOpcode::G_POISON))
           return false;
       }
       return true;

llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h

@@ -428,7 +428,8 @@ struct ImplicitDefMatch {
   bool match(const MachineRegisterInfo &MRI, Register Reg) {
     MachineInstr *TmpMI;
     if (mi_match(Reg, MRI, m_MInstr(TmpMI)))
-      return TmpMI->getOpcode() == TargetOpcode::G_IMPLICIT_DEF;
+      return TmpMI->getOpcode() == TargetOpcode::G_IMPLICIT_DEF ||
+             TmpMI->getOpcode() == TargetOpcode::G_POISON;
     return false;
   }
 };

llvm/include/llvm/Target/GlobalISel/Combine.td

@@ -442,6 +442,7 @@ def unary_undef_to_undef_frags : GICombinePatFrag<
            [G_TRUNC, G_BITCAST, G_ANYEXT, G_PTRTOINT, G_INTTOPTR, G_FPTOSI,
             G_FPTOUI],
            (pattern (op $dst, $x), (G_IMPLICIT_DEF $x)))>;
+
 def unary_undef_to_undef : GICombineRule<
   (defs root:$dst),
   (match (unary_undef_to_undef_frags $dst)),

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

@@ -455,7 +455,7 @@ bool CombinerHelper::matchCombineShuffleConcat(
           return false;
       }
       if (!isLegalOrBeforeLegalizer(
-              {TargetOpcode::G_IMPLICIT_DEF, {ConcatSrcTy}}) ||
+              {TargetOpcode::G_IMPLICIT_DEF, {ConcatSrcTy}}) &&
           !isLegalOrBeforeLegalizer({TargetOpcode::G_POISON, {ConcatSrcTy}}))
         return false;
       Ops.push_back(0);
@@ -2307,7 +2307,8 @@ bool CombinerHelper::matchCombineUnmergeUndef(
       B.buildUndef(DstReg);
     }
   };
-  return isa<GImplicitDef>(MRI.getVRegDef(SrcReg));
+  return isa<GImplicitDef>(MRI.getVRegDef(SrcReg)) ||
+         isa<GPoison>(MRI.getVRegDef(SrcReg));
 }
 
 bool CombinerHelper::matchCombineUnmergeWithDeadLanesToTrunc(
@@ -2733,6 +2734,7 @@ void CombinerHelper::applyCombineTruncOfShift(
 
 bool CombinerHelper::matchAnyExplicitUseIsUndef(MachineInstr &MI) const {
   return any_of(MI.explicit_uses(), [this](const MachineOperand &MO) {
+    // FIXME: Two opcodes should be checked with one call instead.
     return MO.isReg() &&
            (getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MO.getReg(), MRI) ||
             getOpcodeDef(TargetOpcode::G_POISON, MO.getReg(), MRI));
@@ -2770,8 +2772,7 @@ bool CombinerHelper::matchUndefStore(MachineInstr &MI) const {
   assert(MI.getOpcode() == TargetOpcode::G_STORE);
   return getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MI.getOperand(0).getReg(),
                       MRI) ||
-         getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MI.getOperand(0).getReg(),
-                      MRI);
+         getOpcodeDef(TargetOpcode::G_POISON, MI.getOperand(0).getReg(), MRI);
 }
 
 bool CombinerHelper::matchPoisonStore(MachineInstr &MI) const {
@@ -2783,8 +2784,7 @@ bool CombinerHelper::matchUndefSelectCmp(MachineInstr &MI) const {
   assert(MI.getOpcode() == TargetOpcode::G_SELECT);
   return getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MI.getOperand(1).getReg(),
                       MRI) ||
-         getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MI.getOperand(1).getReg(),
-                      MRI);
+         getOpcodeDef(TargetOpcode::G_POISON, MI.getOperand(1).getReg(), MRI);
 }
 
 bool CombinerHelper::matchInsertExtractVecEltOutOfBounds(

llvm/lib/CodeGen/GlobalISel/CombinerHelperVectorOps.cpp

@@ -79,7 +79,8 @@ bool CombinerHelper::matchExtractVectorElement(MachineInstr &MI,
   // Fold extractVectorElement(Vector, TOOLARGE) -> undef
   if (IndexC && VectorTy.isFixedVector() &&
       IndexC->uge(VectorTy.getNumElements()) &&
-      isLegalOrBeforeLegalizer({TargetOpcode::G_IMPLICIT_DEF, {DstTy}})) {
+      (isLegalOrBeforeLegalizer({TargetOpcode::G_IMPLICIT_DEF, {DstTy}}) ||
+       isLegalOrBeforeLegalizer({TargetOpcode::G_POISON, {DstTy}}))) {
     // For fixed-length vectors, it's invalid to extract out-of-range elements.
     MatchInfo = [=](MachineIRBuilder &B) { B.buildUndef(Dst); };
     return true;
@@ -301,7 +302,8 @@ bool CombinerHelper::matchExtractVectorElementWithShuffleVector(
   LLT DstTy = MRI.getType(Dst);
 
   if (SrcIdx < 0 &&
-      isLegalOrBeforeLegalizer({TargetOpcode::G_IMPLICIT_DEF, {DstTy}})) {
+      (isLegalOrBeforeLegalizer({TargetOpcode::G_IMPLICIT_DEF, {DstTy}}) ||
+       isLegalOrBeforeLegalizer({TargetOpcode::G_POISON, {DstTy}}))) {
     MatchInfo = [=](MachineIRBuilder &B) { B.buildUndef(Dst); };
     return true;
   }
@@ -354,7 +356,8 @@ bool CombinerHelper::matchInsertVectorElementOOB(MachineInstr &MI,
       getIConstantVRegValWithLookThrough(Index, MRI);
 
   if (MaybeIndex && MaybeIndex->Value.uge(DstTy.getNumElements()) &&
-      isLegalOrBeforeLegalizer({TargetOpcode::G_IMPLICIT_DEF, {DstTy}})) {
+      (isLegalOrBeforeLegalizer({TargetOpcode::G_IMPLICIT_DEF, {DstTy}}) ||
+       isLegalOrBeforeLegalizer({TargetOpcode::G_POISON, {DstTy}}))) {
     MatchInfo = [=](MachineIRBuilder &B) { B.buildUndef(Dst); };
     return true;
   }

llvm/lib/CodeGen/GlobalISel/Utils.cpp

@@ -1920,6 +1920,7 @@ static bool isGuaranteedNotToBeUndefOrPoison(Register Reg,
   case TargetOpcode::G_FREEZE:
     return true;
   case TargetOpcode::G_POISON:
+    return !includesPoison(Kind);
   case TargetOpcode::G_IMPLICIT_DEF:
     return !includesUndef(Kind);
   case TargetOpcode::G_CONSTANT:

llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp

@@ -453,8 +453,8 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
   // Note: we only write S1 rules for G_IMPLICIT_DEF, G_POISON,
   //                                  G_CONSTANT, G_FCONSTANT
   // and G_FREEZE here, rest is trivially regbankselected earlier
-  addRulesForGOpcs({G_IMPLICIT_DEF, G_POISON})
-      .Any({{UniS1}, {{Sgpr32Trunc}, {}}});
+  addRulesForGOpcs({G_IMPLICIT_DEF}).Any({{UniS1}, {{Sgpr32Trunc}, {}}});
+  addRulesForGOpcs({G_POISON}).Any({{UniS1}, {{Sgpr32Trunc}, {}}});
   addRulesForGOpcs({G_CONSTANT})
       .Any({{UniS1, _}, {{Sgpr32Trunc}, {None}, UniCstExt}});
   addRulesForGOpcs({G_FREEZE}).Any({{DivS1}, {{Vcc}, {Vcc}}});