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jrbyrnesjrbyrnes
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Add test for omitted subrange
Change-Id: I644283266b49b0ccfeb0c6d7b7646865e78db643
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‎llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir‎

Lines changed: 251 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7283,3 +7283,254 @@ body: |
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S_ENDPGM 0
72847284
...
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7286+
# The remat candidate (instruction defining %3) uses a register (%2) which does not have a subrange for every subregister (sub1 is undefined).
7287+
# Be sure that when checking if we can rematerialize %3, that we handle the liveness checking of %2 properly.
7288+
7289+
---
7290+
name: omitted_subrange
7291+
tracksRegLiveness: true
7292+
body: |
7293+
; GFX908-LABEL: name: omitted_subrange
7294+
; GFX908: bb.0:
7295+
; GFX908-NEXT: successors: %bb.1(0x80000000)
7296+
; GFX908-NEXT: liveins: $sgpr3, $sgpr4
7297+
; GFX908-NEXT: {{ $}}
7298+
; GFX908-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
7299+
; GFX908-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
7300+
; GFX908-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
7301+
; GFX908-NEXT: [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
7302+
; GFX908-NEXT: [[DEF4:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
7303+
; GFX908-NEXT: [[DEF5:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
7304+
; GFX908-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
7305+
; GFX908-NEXT: [[DEF7:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
7306+
; GFX908-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
7307+
; GFX908-NEXT: [[DEF9:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
7308+
; GFX908-NEXT: [[DEF10:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
7309+
; GFX908-NEXT: [[DEF11:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
7310+
; GFX908-NEXT: [[DEF12:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
7311+
; GFX908-NEXT: [[DEF13:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
7312+
; GFX908-NEXT: [[DEF14:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
7313+
; GFX908-NEXT: [[DEF15:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
7314+
; GFX908-NEXT: [[DEF16:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
7315+
; GFX908-NEXT: [[DEF17:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
7316+
; GFX908-NEXT: [[DEF18:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
7317+
; GFX908-NEXT: [[DEF19:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
7318+
; GFX908-NEXT: dead [[V_CVT_I32_F32_e32_:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 [[DEF19]], implicit $exec, implicit $mode
7319+
; GFX908-NEXT: [[DEF20:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
7320+
; GFX908-NEXT: [[V_CVT_I32_F32_e32_1:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 [[DEF]], implicit $exec, implicit $mode
7321+
; GFX908-NEXT: [[V_CVT_I32_F32_e32_2:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 [[DEF1]], implicit $exec, implicit $mode
7322+
; GFX908-NEXT: [[V_CVT_I32_F32_e32_3:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 [[DEF2]], implicit $exec, implicit $mode
7323+
; GFX908-NEXT: [[V_CVT_I32_F32_e32_4:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 [[DEF3]], implicit $exec, implicit $mode
7324+
; GFX908-NEXT: [[V_CVT_I32_F32_e32_5:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 [[DEF4]], implicit $exec, implicit $mode
7325+
; GFX908-NEXT: [[V_CVT_I32_F32_e32_6:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 [[DEF5]], implicit $exec, implicit $mode
7326+
; GFX908-NEXT: [[V_CVT_I32_F32_e32_7:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 [[DEF6]], implicit $exec, implicit $mode
7327+
; GFX908-NEXT: [[V_CVT_I32_F32_e32_8:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 [[DEF7]], implicit $exec, implicit $mode
7328+
; GFX908-NEXT: [[V_CVT_I32_F32_e32_9:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 [[DEF8]], implicit $exec, implicit $mode
7329+
; GFX908-NEXT: [[V_CVT_I32_F32_e32_10:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 [[DEF9]], implicit $exec, implicit $mode
7330+
; GFX908-NEXT: [[V_CVT_I32_F32_e32_11:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 [[DEF10]], implicit $exec, implicit $mode
7331+
; GFX908-NEXT: [[V_CVT_I32_F32_e32_12:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 [[DEF11]], implicit $exec, implicit $mode
7332+
; GFX908-NEXT: [[V_CVT_I32_F32_e32_13:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 [[DEF12]], implicit $exec, implicit $mode
7333+
; GFX908-NEXT: [[V_CVT_I32_F32_e32_14:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 [[DEF13]], implicit $exec, implicit $mode
7334+
; GFX908-NEXT: [[V_CVT_I32_F32_e32_15:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 [[DEF14]], implicit $exec, implicit $mode
7335+
; GFX908-NEXT: [[V_CVT_I32_F32_e32_16:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 [[DEF15]], implicit $exec, implicit $mode
7336+
; GFX908-NEXT: [[V_CVT_I32_F32_e32_17:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 [[DEF16]], implicit $exec, implicit $mode
7337+
; GFX908-NEXT: [[V_CVT_I32_F32_e32_18:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 [[DEF17]], implicit $exec, implicit $mode
7338+
; GFX908-NEXT: [[V_CVT_I32_F32_e32_19:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 [[DEF18]], implicit $exec, implicit $mode
7339+
; GFX908-NEXT: [[V_CVT_I32_F32_e32_20:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 [[DEF20]], implicit $exec, implicit $mode
7340+
; GFX908-NEXT: [[DEF21:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
7341+
; GFX908-NEXT: [[V_CVT_I32_F32_e32_21:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 [[DEF21]], implicit $exec, implicit $mode
7342+
; GFX908-NEXT: [[DEF22:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
7343+
; GFX908-NEXT: [[DEF23:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
7344+
; GFX908-NEXT: [[DEF24:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
7345+
; GFX908-NEXT: [[DEF25:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
7346+
; GFX908-NEXT: [[DEF26:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
7347+
; GFX908-NEXT: [[DEF27:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
7348+
; GFX908-NEXT: [[DEF28:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
7349+
; GFX908-NEXT: [[DEF29:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
7350+
; GFX908-NEXT: [[DEF30:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
7351+
; GFX908-NEXT: [[DEF31:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
7352+
; GFX908-NEXT: [[V_CVT_I32_F32_e32_22:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 [[DEF25]], implicit $exec, implicit $mode
7353+
; GFX908-NEXT: [[V_CVT_I32_F32_e32_23:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 [[DEF26]], implicit $exec, implicit $mode
7354+
; GFX908-NEXT: [[V_CVT_I32_F32_e32_24:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 [[DEF27]], implicit $exec, implicit $mode
7355+
; GFX908-NEXT: [[V_CVT_I32_F32_e32_25:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 [[DEF28]], implicit $exec, implicit $mode
7356+
; GFX908-NEXT: [[V_CVT_I32_F32_e32_26:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 [[DEF29]], implicit $exec, implicit $mode
7357+
; GFX908-NEXT: [[V_CVT_I32_F32_e32_27:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 [[DEF30]], implicit $exec, implicit $mode
7358+
; GFX908-NEXT: [[DEF32:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
7359+
; GFX908-NEXT: undef [[V_RCP_F32_e32_:%[0-9]+]].sub0:vreg_64_align2 = nnan ninf nsz arcp contract afn reassoc nofpexcept V_RCP_F32_e32 [[DEF32]].sub0, implicit $mode, implicit $exec
7360+
; GFX908-NEXT: [[V_CVT_I32_F32_e32_28:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 [[DEF31]], implicit $exec, implicit $mode
7361+
; GFX908-NEXT: dead [[DEF33:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
7362+
; GFX908-NEXT: [[V_PK_MUL_F32_:%[0-9]+]]:vreg_64_align2 = nnan ninf nsz arcp contract afn reassoc nofpexcept V_PK_MUL_F32 0, [[V_RCP_F32_e32_]], 8, [[DEF32]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec
7363+
; GFX908-NEXT: [[DEF34:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
7364+
; GFX908-NEXT: S_BRANCH %bb.1
7365+
; GFX908-NEXT: {{ $}}
7366+
; GFX908-NEXT: bb.1:
7367+
; GFX908-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
7368+
; GFX908-NEXT: liveins: $sgpr3, $sgpr4
7369+
; GFX908-NEXT: {{ $}}
7370+
; GFX908-NEXT: %temp:vgpr_32 = IMPLICIT_DEF
7371+
; GFX908-NEXT: S_CMP_LG_U32 $sgpr3, $sgpr4, implicit-def $scc
7372+
; GFX908-NEXT: [[DEF34:%[0-9]+]].sub0:vreg_64_align2 = nnan ninf nsz arcp contract afn reassoc nofpexcept V_MUL_F32_e64 0, [[DEF32]].sub0, 1, %temp, 0, 0, implicit $mode, implicit $exec
7373+
; GFX908-NEXT: S_CBRANCH_SCC1 %bb.2, implicit killed $scc
7374+
; GFX908-NEXT: S_BRANCH %bb.3
7375+
; GFX908-NEXT: {{ $}}
7376+
; GFX908-NEXT: bb.2:
7377+
; GFX908-NEXT: successors: %bb.3(0x80000000)
7378+
; GFX908-NEXT: liveins: $sgpr3, $sgpr4
7379+
; GFX908-NEXT: {{ $}}
7380+
; GFX908-NEXT: undef [[V_FMA_F32_e64_:%[0-9]+]].sub0:vreg_64_align2 = nnan ninf nsz arcp contract afn reassoc nofpexcept V_FMA_F32_e64 0, [[DEF34]].sub1, 0, [[V_RCP_F32_e32_]].sub0, 0, [[DEF34]].sub0, 0, 0, implicit $mode, implicit $exec
7381+
; GFX908-NEXT: %temp2:vreg_64_align2 = IMPLICIT_DEF
7382+
; GFX908-NEXT: dead [[V_PK_FMA_F32_:%[0-9]+]]:vreg_64_align2 = nnan ninf nsz arcp contract afn reassoc nofpexcept V_PK_FMA_F32 0, [[V_FMA_F32_e64_]], 8, %temp2, 11, [[V_PK_MUL_F32_]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec
7383+
; GFX908-NEXT: [[V_CVT_I32_F32_e32_29:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 [[DEF22]], implicit $exec, implicit $mode
7384+
; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F32_e32_29]], implicit [[V_CVT_I32_F32_e32_24]], implicit [[DEF22]], implicit [[DEF27]]
7385+
; GFX908-NEXT: [[V_CVT_I32_F32_e32_30:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 [[DEF23]], implicit $exec, implicit $mode
7386+
; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F32_e32_30]], implicit [[V_CVT_I32_F32_e32_25]], implicit [[DEF23]], implicit [[DEF28]]
7387+
; GFX908-NEXT: [[V_CVT_I32_F32_e32_31:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 [[DEF24]], implicit $exec, implicit $mode
7388+
; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F32_e32_31]], implicit [[V_CVT_I32_F32_e32_26]], implicit [[DEF24]], implicit [[DEF29]]
7389+
; GFX908-NEXT: dead [[DEF35:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
7390+
; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F32_e32_22]], implicit [[V_CVT_I32_F32_e32_27]], implicit [[DEF25]], implicit [[DEF30]]
7391+
; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F32_e32_23]], implicit [[V_CVT_I32_F32_e32_28]], implicit [[DEF26]], implicit [[DEF31]]
7392+
; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F32_e32_1]], implicit [[V_CVT_I32_F32_e32_6]]
7393+
; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F32_e32_2]], implicit [[V_CVT_I32_F32_e32_7]]
7394+
; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F32_e32_3]], implicit [[V_CVT_I32_F32_e32_8]]
7395+
; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F32_e32_4]], implicit [[V_CVT_I32_F32_e32_9]]
7396+
; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F32_e32_5]], implicit [[V_CVT_I32_F32_e32_10]]
7397+
; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F32_e32_11]], implicit [[V_CVT_I32_F32_e32_12]]
7398+
; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F32_e32_13]], implicit [[V_CVT_I32_F32_e32_14]]
7399+
; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F32_e32_13]], implicit [[V_CVT_I32_F32_e32_14]]
7400+
; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F32_e32_15]], implicit [[V_CVT_I32_F32_e32_16]]
7401+
; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F32_e32_17]], implicit [[V_CVT_I32_F32_e32_18]]
7402+
; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F32_e32_19]], implicit [[V_CVT_I32_F32_e32_20]]
7403+
; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F32_e32_21]]
7404+
; GFX908-NEXT: S_BRANCH %bb.3
7405+
; GFX908-NEXT: {{ $}}
7406+
; GFX908-NEXT: bb.3:
7407+
; GFX908-NEXT: successors: %bb.1(0x40000000), %bb.4(0x40000000)
7408+
; GFX908-NEXT: liveins: $sgpr3, $sgpr4
7409+
; GFX908-NEXT: {{ $}}
7410+
; GFX908-NEXT: S_CMP_LG_U32 $sgpr4, 0, implicit-def $scc
7411+
; GFX908-NEXT: S_CBRANCH_SCC1 %bb.1, implicit killed $scc
7412+
; GFX908-NEXT: S_BRANCH %bb.4
7413+
; GFX908-NEXT: {{ $}}
7414+
; GFX908-NEXT: bb.4:
7415+
; GFX908-NEXT: S_ENDPGM 0
7416+
bb.0:
7417+
liveins: $sgpr3, $sgpr4
7418+
7419+
%0:vreg_64 = IMPLICIT_DEF
7420+
%1:vreg_64_align2 = IMPLICIT_DEF
7421+
undef %2.sub0:vreg_64_align2 = nnan ninf nsz arcp contract afn reassoc nofpexcept V_RCP_F32_e32 %1.sub0:vreg_64_align2, implicit $mode, implicit $exec
7422+
%3:vreg_64_align2 = nnan ninf nsz arcp contract afn reassoc nofpexcept V_PK_MUL_F32 0, %2, 8, %1, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
7423+
%5:vreg_64_align2 = IMPLICIT_DEF
7424+
%10:vgpr_32 = IMPLICIT_DEF
7425+
%11:vgpr_32 = IMPLICIT_DEF
7426+
%12:vgpr_32 = IMPLICIT_DEF
7427+
%13:vgpr_32 = IMPLICIT_DEF
7428+
%14:vgpr_32 = IMPLICIT_DEF
7429+
%15:vgpr_32 = IMPLICIT_DEF
7430+
%16:vgpr_32 = IMPLICIT_DEF
7431+
%17:vgpr_32 = IMPLICIT_DEF
7432+
%18:vgpr_32 = IMPLICIT_DEF
7433+
%19:vgpr_32 = IMPLICIT_DEF
7434+
%20:vgpr_32 = IMPLICIT_DEF
7435+
%21:vgpr_32 = IMPLICIT_DEF
7436+
%22:vgpr_32 = IMPLICIT_DEF
7437+
%23:vgpr_32 = IMPLICIT_DEF
7438+
%24:vgpr_32 = IMPLICIT_DEF
7439+
%25:vgpr_32 = IMPLICIT_DEF
7440+
%26:vgpr_32 = IMPLICIT_DEF
7441+
%27:vgpr_32 = IMPLICIT_DEF
7442+
%28:vgpr_32 = IMPLICIT_DEF
7443+
%29:vgpr_32 = IMPLICIT_DEF
7444+
%30:vgpr_32 = IMPLICIT_DEF
7445+
%31:vgpr_32 = IMPLICIT_DEF
7446+
%32:vgpr_32 = IMPLICIT_DEF
7447+
%33:vgpr_32 = IMPLICIT_DEF
7448+
%34:vgpr_32 = IMPLICIT_DEF
7449+
%35:vgpr_32 = IMPLICIT_DEF
7450+
%36:vgpr_32 = IMPLICIT_DEF
7451+
%37:vgpr_32 = IMPLICIT_DEF
7452+
%38:vgpr_32 = IMPLICIT_DEF
7453+
%39:vgpr_32 = IMPLICIT_DEF
7454+
%40:vgpr_32 = IMPLICIT_DEF
7455+
%41:vgpr_32 = IMPLICIT_DEF
7456+
%50:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %10, implicit $exec, implicit $mode
7457+
%51:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %11, implicit $exec, implicit $mode
7458+
%52:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %12, implicit $exec, implicit $mode
7459+
%53:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %13, implicit $exec, implicit $mode
7460+
%54:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %14, implicit $exec, implicit $mode
7461+
%55:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %15, implicit $exec, implicit $mode
7462+
%56:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %16, implicit $exec, implicit $mode
7463+
%57:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %17, implicit $exec, implicit $mode
7464+
%58:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %18, implicit $exec, implicit $mode
7465+
%59:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %19, implicit $exec, implicit $mode
7466+
%60:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %20, implicit $exec, implicit $mode
7467+
%61:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %21, implicit $exec, implicit $mode
7468+
%62:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %22, implicit $exec, implicit $mode
7469+
%63:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %23, implicit $exec, implicit $mode
7470+
%64:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %24, implicit $exec, implicit $mode
7471+
%65:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %25, implicit $exec, implicit $mode
7472+
%66:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %26, implicit $exec, implicit $mode
7473+
%67:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %27, implicit $exec, implicit $mode
7474+
%68:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %28, implicit $exec, implicit $mode
7475+
%69:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %29, implicit $exec, implicit $mode
7476+
%70:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %30, implicit $exec, implicit $mode
7477+
%71:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %31, implicit $exec, implicit $mode
7478+
%72:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %32, implicit $exec, implicit $mode
7479+
%73:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %33, implicit $exec, implicit $mode
7480+
%74:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %34, implicit $exec, implicit $mode
7481+
%75:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %35, implicit $exec, implicit $mode
7482+
%76:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %36, implicit $exec, implicit $mode
7483+
%77:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %37, implicit $exec, implicit $mode
7484+
%78:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %38, implicit $exec, implicit $mode
7485+
%79:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %39, implicit $exec, implicit $mode
7486+
%80:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %40, implicit $exec, implicit $mode
7487+
%81:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %41, implicit $exec, implicit $mode
7488+
S_BRANCH %bb.1
7489+
7490+
bb.1:
7491+
liveins: $sgpr3, $sgpr4
7492+
7493+
%temp:vgpr_32 = IMPLICIT_DEF
7494+
%5.sub0:vreg_64_align2 = nnan ninf nsz arcp contract afn reassoc nofpexcept V_MUL_F32_e64 0, %1.sub0:vreg_64_align2, 1, %temp, 0, 0, implicit $mode, implicit $exec
7495+
7496+
S_CMP_LG_U32 killed $sgpr3, $sgpr4, implicit-def $scc
7497+
S_CBRANCH_SCC1 %bb.3, implicit killed $scc
7498+
S_BRANCH %bb.4
7499+
7500+
bb.3:
7501+
liveins: $sgpr3, $sgpr4
7502+
7503+
%6:vreg_64_align2 = IMPLICIT_DEF
7504+
undef %7.sub0:vreg_64_align2 = nnan ninf nsz arcp contract afn reassoc nofpexcept V_FMA_F32_e64 0, %5.sub1, 0, %2.sub0:vreg_64_align2, 0, %5.sub0:vreg_64_align2, 0, 0, implicit $mode, implicit $exec
7505+
%temp2:vreg_64_align2 = IMPLICIT_DEF
7506+
%8:vreg_64_align2 = nnan ninf nsz arcp contract afn reassoc nofpexcept V_PK_FMA_F32 0, %7:vreg_64_align2, 8, %temp2, 11, %3:vreg_64_align2, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
7507+
S_NOP 0, implicit %50, implicit %60, implicit %10, implicit %20
7508+
S_NOP 0, implicit %51, implicit %61, implicit %11, implicit %21
7509+
S_NOP 0, implicit %52, implicit %62, implicit %12, implicit %22
7510+
S_NOP 0, implicit %53, implicit %63, implicit %13, implicit %23
7511+
S_NOP 0, implicit %54, implicit %64, implicit %14, implicit %24
7512+
S_NOP 0, implicit %55, implicit %65
7513+
S_NOP 0, implicit %56, implicit %66
7514+
S_NOP 0, implicit %57, implicit %67
7515+
S_NOP 0, implicit %58, implicit %68
7516+
S_NOP 0, implicit %59, implicit %69
7517+
S_NOP 0, implicit %70, implicit %71
7518+
S_NOP 0, implicit %72, implicit %73
7519+
S_NOP 0, implicit %72, implicit %73
7520+
S_NOP 0, implicit %74, implicit %75
7521+
S_NOP 0, implicit %76, implicit %77
7522+
S_NOP 0, implicit %78, implicit %79
7523+
S_NOP 0, implicit %80
7524+
S_BRANCH %bb.4
7525+
7526+
bb.4:
7527+
liveins: $sgpr3, $sgpr4
7528+
7529+
S_CMP_LG_U32 $sgpr4, 0, implicit-def $scc
7530+
S_CBRANCH_SCC1 %bb.1, implicit killed $scc
7531+
S_BRANCH %bb.2
7532+
7533+
bb.2:
7534+
S_ENDPGM 0
7535+
7536+
...

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