Dropped all the LLT references.

Author: dhruvachak

llvm/test/CodeGen/AMDGPU/schedule-regpressure-no-unclustered-regions.mir

@@ -27,18 +27,18 @@ body:             |
     liveins: $vgpr0, $sgpr0_sgpr1, $sgpr15
 
     %0:sgpr_32 = COPY $sgpr15
-    %1:sgpr_64(p4) = COPY $sgpr0_sgpr1
-    %2:vgpr_32(s32) = COPY $vgpr0
-    %3:sgpr_128 = S_LOAD_DWORDX4_IMM %1(p4), 0, 0 :: (dereferenceable invariant load (s128), addrspace 4)
-    undef %4.sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM %1(p4), 16, 0 :: (dereferenceable invariant load (s64), align 16, addrspace 4)
-    %5:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %1(p4), 32, 0 :: (dereferenceable invariant load (s32), align 8, addrspace 4)
-    %6:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %1(p4), 64, 0 :: (dereferenceable invariant load (s32), align 8, addrspace 4)
-    %7:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %1(p4), 84, 0 :: (dereferenceable invariant load (s32), addrspace 4)
-    %8:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %1(p4), 112, 0 :: (dereferenceable invariant load (s32), align 8, addrspace 4)
-    %9:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %1(p4), 128, 0 :: (dereferenceable invariant load (s32), align 8, addrspace 4)
-    %10:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %1(p4), 176, 0 :: (dereferenceable invariant load (s32), align 8, addrspace 4)
-    %11:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %1(p4), 192, 0 :: (dereferenceable invariant load (s32), align 8, addrspace 4)
-    %12:sreg_64_xexec = S_LOAD_DWORDX2_IMM %1(p4), 216, 0 :: (dereferenceable invariant load (s64), addrspace 4)
+    %1:sgpr_64 = COPY $sgpr0_sgpr1
+    %2:vgpr_32 = COPY $vgpr0
+    %3:sgpr_128 = S_LOAD_DWORDX4_IMM %1, 0, 0 :: (dereferenceable invariant load (s128), addrspace 4)
+    undef %4.sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM %1, 16, 0 :: (dereferenceable invariant load (s64), align 16, addrspace 4)
+    %5:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %1, 32, 0 :: (dereferenceable invariant load (s32), align 8, addrspace 4)
+    %6:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %1, 64, 0 :: (dereferenceable invariant load (s32), align 8, addrspace 4)
+    %7:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %1, 84, 0 :: (dereferenceable invariant load (s32), addrspace 4)
+    %8:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %1, 112, 0 :: (dereferenceable invariant load (s32), align 8, addrspace 4)
+    %9:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %1, 128, 0 :: (dereferenceable invariant load (s32), align 8, addrspace 4)
+    %10:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %1, 176, 0 :: (dereferenceable invariant load (s32), align 8, addrspace 4)
+    %11:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %1, 192, 0 :: (dereferenceable invariant load (s32), align 8, addrspace 4)
+    %12:sreg_64_xexec = S_LOAD_DWORDX2_IMM %1, 216, 0 :: (dereferenceable invariant load (s64), addrspace 4)
     %13:sreg_32 = S_ADD_I32 %12.sub0, 127, implicit-def dead $scc
     %14:sreg_32 = S_ASHR_I32 %13, 31, implicit-def dead $scc
     %15:sreg_32 = S_LSHR_B32 %14, 25, implicit-def dead $scc
@@ -188,25 +188,25 @@ body:             |
     %148:sreg_32 = S_ADD_I32 %147, %146, implicit-def dead $scc
     %149:sreg_32 = S_LSHL_B32 %148, 7, implicit-def dead $scc
     %150:sreg_32 = nsw S_LSHL_B32 %144, 8, implicit-def dead $scc
-    %151:vgpr_32 = nuw nsw V_LSHLREV_B32_e64 1, %2(s32), implicit $exec
+    %151:vgpr_32 = nuw nsw V_LSHLREV_B32_e64 1, %2, implicit $exec
     %152:vgpr_32 = V_AND_B32_e64 6, %151, implicit $exec
-    %153:vgpr_32 = V_LSHRREV_B32_e64 1, %2(s32), implicit $exec
+    %153:vgpr_32 = V_LSHRREV_B32_e64 1, %2, implicit $exec
     %154:vgpr_32 = V_AND_B32_e64 126, %153, implicit $exec
     %155:vgpr_32 = nsw V_ADD_U32_e64 %149, %154, 0, implicit $exec
     undef %156.sub0:vreg_64 = nuw nsw V_LSHLREV_B32_e64 3, %152, implicit $exec
     early-clobber %157:vreg_64, $sgpr_null = V_MAD_U64_U32_gfx11_e64 %155, %5, %156, 0, implicit $exec
     %158:vgpr_32 = V_MUL_U32_U24_e64 1032, %152, 0, implicit $exec
     %159:vgpr_32 = nuw nsw V_LSHLREV_B32_e64 3, %154, implicit $exec
-    %160:vgpr_32 = V_AND_B32_e64 252, %2(s32), implicit $exec
+    %160:vgpr_32 = V_AND_B32_e64 252, %2, implicit $exec
     %161:vgpr_32 = nsw V_ADD_U32_e64 %150, %160, 0, implicit $exec
     early-clobber %162:vreg_64, $sgpr_null = V_MAD_U64_U32_gfx11_e64 %161, %7, %156, 0, implicit $exec
     %163:vgpr_32 = V_MUL_U32_U24_e64 2056, %152, 0, implicit $exec
     %164:vgpr_32 = nuw nsw V_LSHLREV_B32_e64 3, %160, implicit $exec
-    %165:vgpr_32 = nuw nsw V_LSHLREV_B32_e64 3, %2(s32), implicit $exec
-    %166:vgpr_32 = V_BFE_U32_e64 %2(s32), 1, 3, implicit $exec
+    %165:vgpr_32 = nuw nsw V_LSHLREV_B32_e64 3, %2, implicit $exec
+    %166:vgpr_32 = V_BFE_U32_e64 %2, 1, 3, implicit $exec
     %167:vgpr_32 = V_AND_OR_B32_e64 %165, 8, %166, implicit $exec
-    %168:vgpr_32 = V_AND_B32_e64 128, %2(s32), implicit $exec
-    %169:vgpr_32 = V_AND_B32_e64 15, %2(s32), implicit $exec
+    %168:vgpr_32 = V_AND_B32_e64 128, %2, implicit $exec
+    %169:vgpr_32 = V_AND_B32_e64 15, %2, implicit $exec
     %170:vgpr_32 = V_AND_OR_B32_e64 %153, 48, %169, implicit $exec
     undef %171.sub2:sgpr_128 = S_LSHL_B32 %6, 1, implicit-def dead $scc
     %171.sub3:sgpr_128 = S_MOV_B32 268566528
@@ -397,7 +397,7 @@ body:             |
     early-clobber %212:vreg_256 = V_WMMA_F32_16X16X16_F16_twoaddr_w32 8, %229, 8, %231, 8, %212, 0, 0, implicit $exec
     early-clobber %212:vreg_256 = V_WMMA_F32_16X16X16_F16_twoaddr_w32 8, %237, 8, %239, 8, %212, 0, 0, implicit $exec
     early-clobber %252:vreg_256 = V_WMMA_F32_16X16X16_F16_twoaddr_w32 8, %244, 8, %241, 8, %252, 0, 0, implicit $exec
-    %254:vgpr_32 = V_LSHRREV_B32_e64 3, %2(s32), implicit $exec
+    %254:vgpr_32 = V_LSHRREV_B32_e64 3, %2, implicit $exec
     %255:vgpr_32 = V_AND_B32_e64 8, %153, implicit $exec
     %256:vgpr_32 = V_AND_OR_B32_e64 %254, 16, %255, implicit $exec
     %257:vgpr_32 = V_AND_B32_e64 56, %165, implicit $exec