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[NVPTX] Add syncscope support for cmpxchg
1 parent 743571b commit 38db2d3

18 files changed

+47182
-7377
lines changed

‎llvm/include/llvm/CodeGen/TargetLowering.h‎

Lines changed: 9 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -2286,13 +2286,15 @@ class TargetLoweringBase {
22862286
/// standard ABI uses a fence before a seq_cst load instead of after a
22872287
/// seq_cst store).
22882288
/// @{
2289-
virtual Instruction *emitLeadingFence(IRBuilderBase &Builder,
2290-
Instruction *Inst,
2291-
AtomicOrdering Ord) const;
2292-
2293-
virtual Instruction *emitTrailingFence(IRBuilderBase &Builder,
2294-
Instruction *Inst,
2295-
AtomicOrdering Ord) const;
2289+
virtual Instruction *
2290+
emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst,
2291+
AtomicOrdering Ord,
2292+
SyncScope::ID SSID = SyncScope::System) const;
2293+
2294+
virtual Instruction *
2295+
emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst,
2296+
AtomicOrdering Ord,
2297+
SyncScope::ID SSID = SyncScope::System) const;
22962298
/// @}
22972299

22982300
// Emits code that executes when the comparison result in the ll/sc

‎llvm/lib/CodeGen/AtomicExpandPass.cpp‎

Lines changed: 13 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -65,7 +65,8 @@ class AtomicExpandImpl {
6565
const DataLayout *DL = nullptr;
6666

6767
private:
68-
bool bracketInstWithFences(Instruction *I, AtomicOrdering Order);
68+
bool bracketInstWithFences(Instruction *I, AtomicOrdering Order,
69+
SyncScope::ID SSID = SyncScope::System);
6970
IntegerType *getCorrespondingIntegerType(Type *T, const DataLayout &DL);
7071
LoadInst *convertAtomicLoadToIntegerType(LoadInst *LI);
7172
bool tryExpandAtomicLoad(LoadInst *LI);
@@ -303,6 +304,7 @@ bool AtomicExpandImpl::processAtomicInstr(Instruction *I) {
303304

304305
if (TLI->shouldInsertFencesForAtomic(I)) {
305306
auto FenceOrdering = AtomicOrdering::Monotonic;
307+
SyncScope::ID SSID = SyncScope::System;
306308
if (LI && isAcquireOrStronger(LI->getOrdering())) {
307309
FenceOrdering = LI->getOrdering();
308310
LI->setOrdering(AtomicOrdering::Monotonic);
@@ -325,13 +327,18 @@ bool AtomicExpandImpl::processAtomicInstr(Instruction *I) {
325327
// expandAtomicCmpXchg in that case.
326328
FenceOrdering = CASI->getMergedOrdering();
327329
auto CASOrdering = TLI->atomicOperationOrderAfterFenceSplit(CASI);
330+
SSID = CASI->getSyncScopeID();
328331

329332
CASI->setSuccessOrdering(CASOrdering);
330333
CASI->setFailureOrdering(CASOrdering);
334+
// If CAS ordering is monotonic, then the operation will
335+
// take default scope. Otherwise, it will retain its scope
336+
if (CASOrdering != AtomicOrdering::Monotonic)
337+
CASI->setSyncScopeID(SSID);
331338
}
332339

333340
if (FenceOrdering != AtomicOrdering::Monotonic) {
334-
MadeChange |= bracketInstWithFences(I, FenceOrdering);
341+
MadeChange |= bracketInstWithFences(I, FenceOrdering, SSID);
335342
}
336343
} else if (I->hasAtomicStore() &&
337344
TLI->shouldInsertTrailingFenceForAtomicStore(I)) {
@@ -432,12 +439,13 @@ PreservedAnalyses AtomicExpandPass::run(Function &F,
432439
}
433440

434441
bool AtomicExpandImpl::bracketInstWithFences(Instruction *I,
435-
AtomicOrdering Order) {
442+
AtomicOrdering Order,
443+
SyncScope::ID SSID) {
436444
ReplacementIRBuilder Builder(I, *DL);
437445

438-
auto LeadingFence = TLI->emitLeadingFence(Builder, I, Order);
446+
auto LeadingFence = TLI->emitLeadingFence(Builder, I, Order, SSID);
439447

440-
auto TrailingFence = TLI->emitTrailingFence(Builder, I, Order);
448+
auto TrailingFence = TLI->emitTrailingFence(Builder, I, Order, SSID);
441449
// We have a guard here because not every atomic operation generates a
442450
// trailing fence.
443451
if (TrailingFence)

‎llvm/lib/CodeGen/TargetLoweringBase.cpp‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2320,18 +2320,20 @@ TargetLoweringBase::getAtomicMemOperandFlags(const Instruction &AI,
23202320

23212321
Instruction *TargetLoweringBase::emitLeadingFence(IRBuilderBase &Builder,
23222322
Instruction *Inst,
2323-
AtomicOrdering Ord) const {
2323+
AtomicOrdering Ord,
2324+
SyncScope::ID SSID) const {
23242325
if (isReleaseOrStronger(Ord) && Inst->hasAtomicStore())
2325-
return Builder.CreateFence(Ord);
2326+
return Builder.CreateFence(Ord, SSID);
23262327
else
23272328
return nullptr;
23282329
}
23292330

23302331
Instruction *TargetLoweringBase::emitTrailingFence(IRBuilderBase &Builder,
23312332
Instruction *Inst,
2332-
AtomicOrdering Ord) const {
2333+
AtomicOrdering Ord,
2334+
SyncScope::ID SSID) const {
23332335
if (isAcquireOrStronger(Ord))
2334-
return Builder.CreateFence(Ord);
2336+
return Builder.CreateFence(Ord, SSID);
23352337
else
23362338
return nullptr;
23372339
}

‎llvm/lib/Target/ARM/ARMISelLowering.cpp‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -21221,7 +21221,8 @@ Instruction *ARMTargetLowering::makeDMB(IRBuilderBase &Builder,
2122121221
// Based on http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
2122221222
Instruction *ARMTargetLowering::emitLeadingFence(IRBuilderBase &Builder,
2122321223
Instruction *Inst,
21224-
AtomicOrdering Ord) const {
21224+
AtomicOrdering Ord,
21225+
SyncScope::ID SSID) const {
2122521226
switch (Ord) {
2122621227
case AtomicOrdering::NotAtomic:
2122721228
case AtomicOrdering::Unordered:
@@ -21246,7 +21247,8 @@ Instruction *ARMTargetLowering::emitLeadingFence(IRBuilderBase &Builder,
2124621247

2124721248
Instruction *ARMTargetLowering::emitTrailingFence(IRBuilderBase &Builder,
2124821249
Instruction *Inst,
21249-
AtomicOrdering Ord) const {
21250+
AtomicOrdering Ord,
21251+
SyncScope::ID SSID) const {
2125021252
switch (Ord) {
2125121253
case AtomicOrdering::NotAtomic:
2125221254
case AtomicOrdering::Unordered:

‎llvm/lib/Target/ARM/ARMISelLowering.h‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -666,10 +666,12 @@ class VectorType;
666666
void
667667
emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) const override;
668668

669-
Instruction *emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst,
670-
AtomicOrdering Ord) const override;
671-
Instruction *emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst,
672-
AtomicOrdering Ord) const override;
669+
Instruction *emitLeadingFence(
670+
IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord,
671+
SyncScope::ID SSID = SyncScope::ID SyncScope::System) const override;
672+
Instruction *emitTrailingFence(
673+
IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord,
674+
SyncScope::ID SSID = SyncScope::ID SyncScope::System) const override;
673675

674676
unsigned getMaxSupportedInterleaveFactor() const override;
675677

‎llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp‎

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -6055,23 +6055,26 @@ AtomicOrdering NVPTXTargetLowering::atomicOperationOrderAfterFenceSplit(
60556055

60566056
Instruction *NVPTXTargetLowering::emitLeadingFence(IRBuilderBase &Builder,
60576057
Instruction *Inst,
6058-
AtomicOrdering Ord) const {
6058+
AtomicOrdering Ord,
6059+
SyncScope::ID SSID) const {
60596060
if (!isa<AtomicCmpXchgInst>(Inst))
60606061
return TargetLoweringBase::emitLeadingFence(Builder, Inst, Ord);
60616062

60626063
// Specialize for cmpxchg
60636064
// Emit a fence.sc leading fence for cmpxchg seq_cst which are not emulated
60646065
if (isReleaseOrStronger(Ord))
60656066
return Ord == AtomicOrdering::SequentiallyConsistent
6066-
? Builder.CreateFence(AtomicOrdering::SequentiallyConsistent)
6067-
: Builder.CreateFence(AtomicOrdering::Release);
6067+
? Builder.CreateFence(AtomicOrdering::SequentiallyConsistent,
6068+
SSID)
6069+
: Builder.CreateFence(AtomicOrdering::Release, SSID);
60686070

60696071
return nullptr;
60706072
}
60716073

60726074
Instruction *NVPTXTargetLowering::emitTrailingFence(IRBuilderBase &Builder,
60736075
Instruction *Inst,
6074-
AtomicOrdering Ord) const {
6076+
AtomicOrdering Ord,
6077+
SyncScope::ID SSID) const {
60756078
// Specialize for cmpxchg
60766079
if (!isa<AtomicCmpXchgInst>(Inst))
60776080
return TargetLoweringBase::emitTrailingFence(Builder, Inst, Ord);
@@ -6084,7 +6087,7 @@ Instruction *NVPTXTargetLowering::emitTrailingFence(IRBuilderBase &Builder,
60846087
if (isAcquireOrStronger(Ord) &&
60856088
(Ord != AtomicOrdering::SequentiallyConsistent ||
60866089
CASWidth < STI.getMinCmpXchgSizeInBits()))
6087-
return Builder.CreateFence(AtomicOrdering::Acquire);
6090+
return Builder.CreateFence(AtomicOrdering::Acquire, SSID);
60886091

60896092
return nullptr;
60906093
}

‎llvm/lib/Target/NVPTX/NVPTXISelLowering.h‎

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -266,10 +266,14 @@ class NVPTXTargetLowering : public TargetLowering {
266266
AtomicOrdering
267267
atomicOperationOrderAfterFenceSplit(const Instruction *I) const override;
268268

269-
Instruction *emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst,
270-
AtomicOrdering Ord) const override;
271-
Instruction *emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst,
272-
AtomicOrdering Ord) const override;
269+
Instruction *
270+
emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst,
271+
AtomicOrdering Ord,
272+
SyncScope::ID SSID = SyncScope::System) const override;
273+
Instruction *
274+
emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst,
275+
AtomicOrdering Ord,
276+
SyncScope::ID SSID = SyncScope::System) const override;
273277

274278
private:
275279
const NVPTXSubtarget &STI; // cache the subtarget here

‎llvm/lib/Target/NVPTX/NVPTXIntrinsics.td‎

Lines changed: 50 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -38,6 +38,27 @@ def AS_match {
3838
}];
3939
}
4040

41+
multiclass nvvm_ternary_atomic_op_scoped<SDPatternOperator frag> {
42+
defvar frag_pat = (frag node:$ptr, node:$cmp, node:$val);
43+
def NAME#_cta: PatFrag<!setdagop(frag_pat, ops),
44+
(!cast<SDPatternOperator>(NAME) node:$ptr, node:$cmp, node:$val), [{
45+
return Scopes[cast<MemSDNode>(N)->getSyncScopeID()] == NVPTX::Scope::Block;
46+
}]>;
47+
def NAME#_cluster : PatFrag<!setdagop(frag_pat, ops),
48+
(!cast<SDPatternOperator>(NAME) node:$ptr, node:$cmp, node:$val), [{
49+
return Scopes[cast<MemSDNode>(N)->getSyncScopeID()] == NVPTX::Scope::Cluster;
50+
}]>;
51+
def NAME#_gpu: PatFrag<!setdagop(frag_pat, ops),
52+
(!cast<SDPatternOperator>(NAME) node:$ptr, node:$cmp, node:$val), [{
53+
return Scopes[cast<MemSDNode>(N)->getSyncScopeID()] == NVPTX::Scope::Device;
54+
}]>;
55+
def NAME#_sys: PatFrag<!setdagop(frag_pat, ops),
56+
(!cast<SDPatternOperator>(NAME) node:$ptr, node:$cmp, node:$val), [{
57+
return Scopes[cast<MemSDNode>(N)->getSyncScopeID()] == NVPTX::Scope::System;
58+
}]>;
59+
}
60+
61+
4162
// A node that will be replaced with the current PTX version.
4263
class PTX {
4364
SDNodeXForm PTXVerXform = SDNodeXForm<imm, [{
@@ -2022,40 +2043,41 @@ multiclass F_ATOMIC_2_NEG<ValueType regT, NVPTXRegClass regclass, string SpaceSt
20222043

20232044
// has 3 operands
20242045
multiclass F_ATOMIC_3_imp<ValueType ptrT, NVPTXRegClass ptrclass,
2025-
ValueType regT, NVPTXRegClass regclass, string SemStr,
2026-
string SpaceStr, string TypeStr, string OpcStr, PatFrag IntOp,
2027-
Operand IMMType, list<Predicate> Pred> {
2046+
ValueType regT, NVPTXRegClass regclass, string SemStr,
2047+
string ScopeStr, string SpaceStr, string TypeStr, string OpcStr,
2048+
PatFrag IntOp, Operand IMMType, list<Predicate> Pred> {
20282049
let mayLoad = 1, mayStore = 1, hasSideEffects = 1 in {
20292050
def reg : NVPTXInst<(outs regclass:$dst),
20302051
(ins ptrclass:$addr, regclass:$b, regclass:$c),
2031-
!strconcat("atom", SemStr, SpaceStr, OpcStr, TypeStr, " \t$dst, [$addr], $b, $c;"),
2052+
!strconcat("atom", SemStr, ScopeStr, SpaceStr, OpcStr, TypeStr, " \t$dst, [$addr], $b, $c;"),
20322053
[(set (regT regclass:$dst), (IntOp (ptrT ptrclass:$addr), (regT regclass:$b), (regT regclass:$c)))]>,
20332054
Requires<Pred>;
20342055

20352056
def imm1 : NVPTXInst<(outs regclass:$dst),
20362057
(ins ptrclass:$addr, IMMType:$b, regclass:$c),
2037-
!strconcat("atom", SemStr, SpaceStr, OpcStr, TypeStr, " \t$dst, [$addr], $b, $c;"),
2058+
!strconcat("atom", SemStr, ScopeStr, SpaceStr, OpcStr, TypeStr, " \t$dst, [$addr], $b, $c;"),
20382059
[(set (regT regclass:$dst), (IntOp (ptrT ptrclass:$addr), imm:$b, (regT regclass:$c)))]>,
20392060
Requires<Pred>;
20402061

20412062
def imm2 : NVPTXInst<(outs regclass:$dst),
20422063
(ins ptrclass:$addr, regclass:$b, IMMType:$c),
2043-
!strconcat("atom", SemStr, SpaceStr, OpcStr, TypeStr, " \t$dst, [$addr], $b, $c;", ""),
2064+
!strconcat("atom", SemStr, ScopeStr, SpaceStr, OpcStr, TypeStr, " \t$dst, [$addr], $b, $c;", ""),
20442065
[(set (regT regclass:$dst), (IntOp (ptrT ptrclass:$addr), (regT regclass:$b), imm:$c))]>,
20452066
Requires<Pred>;
20462067

20472068
def imm3 : NVPTXInst<(outs regclass:$dst),
20482069
(ins ptrclass:$addr, IMMType:$b, IMMType:$c),
2049-
!strconcat("atom", SemStr, SpaceStr, OpcStr, TypeStr, " \t$dst, [$addr], $b, $c;"),
2070+
!strconcat("atom", SemStr, ScopeStr, SpaceStr, OpcStr, TypeStr, " \t$dst, [$addr], $b, $c;"),
20502071
[(set (regT regclass:$dst), (IntOp (ptrT ptrclass:$addr), imm:$b, imm:$c))]>,
20512072
Requires<Pred>;
20522073
}
20532074
}
2054-
multiclass F_ATOMIC_3<ValueType regT, NVPTXRegClass regclass, string SemStr, string SpaceStr,
2055-
string TypeStr, string OpcStr, PatFrag IntOp, Operand IMMType, list<Predicate> Pred = []> {
2056-
defm p32 : F_ATOMIC_3_imp<i32, Int32Regs, regT, regclass, SemStr, SpaceStr, TypeStr,
2075+
multiclass F_ATOMIC_3<ValueType regT, NVPTXRegClass regclass, string SemStr, string ScopeStr,
2076+
string SpaceStr, string TypeStr, string OpcStr, PatFrag IntOp, Operand IMMType,
2077+
list<Predicate> Pred = []> {
2078+
defm p32 : F_ATOMIC_3_imp<i32, Int32Regs, regT, regclass, SemStr, ScopeStr, SpaceStr, TypeStr,
20572079
OpcStr, IntOp, IMMType, Pred>;
2058-
defm p64 : F_ATOMIC_3_imp<i64, Int64Regs, regT, regclass, SemStr, SpaceStr, TypeStr,
2080+
defm p64 : F_ATOMIC_3_imp<i64, Int64Regs, regT, regclass, SemStr, ScopeStr, SpaceStr, TypeStr,
20592081
OpcStr, IntOp, IMMType, Pred>;
20602082
}
20612083

@@ -2469,10 +2491,12 @@ foreach size = ["i16", "i32", "i64"] in {
24692491
// ".cas", atomic_cmp_swap_i32_acquire_global, i32imm,
24702492
// [hasSM<70>, hasPTX<63>]>
24712493
multiclass INT_PTX_ATOM_CAS<string atomic_cmp_swap_pat, string type,
2472-
string order, string addrspace, list<Predicate> preds>
2494+
string order, string scope, string addrspace,
2495+
list<Predicate> preds>
24732496
: F_ATOMIC_3<!cast<ValueType>("i"#type),
24742497
!cast<NVPTXRegClass>("Int"#type#"Regs"),
24752498
order,
2499+
scope,
24762500
addrspace,
24772501
".b"#type,
24782502
".cas",
@@ -2487,26 +2511,35 @@ foreach size = ["32", "64"] in {
24872511
defvar cas_addrspace_string = !if(!eq(addrspace, "generic"), "", "."#addrspace);
24882512
foreach order = ["acquire", "release", "acq_rel", "monotonic"] in {
24892513
defvar cas_order_string = !if(!eq(order, "monotonic"), ".relaxed", "."#order);
2514+
defvar atomic_cmp_swap_pat = !cast<PatFrag>("atomic_cmp_swap_i"#size#_#order#_#addrspace);
2515+
defm atomic_cmp_swap_i#size#_#order#_#addrspace: nvvm_ternary_atomic_op_scoped<atomic_cmp_swap_pat>;
2516+
2517+
foreach scope = ["cta", "cluster", "gpu", "sys"] in {
2518+
defm INT_PTX_ATOM_CAS_#size#_#order#addrspace#scope
2519+
: INT_PTX_ATOM_CAS<"atomic_cmp_swap_i"#size#_#order#_#addrspace#_#scope, size,
2520+
cas_order_string, "."#scope, cas_addrspace_string,
2521+
[hasSM<70>, hasPTX<63>]>;
2522+
}
24902523
// Note that AtomicExpand will convert cmpxchg seq_cst to a cmpxchg monotonic with fences around it.
24912524
// Memory orders are only supported for SM70+, PTX63+- so we have two sets of instruction definitions-
24922525
// for SM70+, and "old" ones which lower to "atom.cas", for earlier archs.
24932526
defm INT_PTX_ATOM_CAS_#size#_#order#addrspace
24942527
: INT_PTX_ATOM_CAS<"atomic_cmp_swap_i"#size#_#order#_#addrspace, size,
2495-
cas_order_string, cas_addrspace_string,
2528+
cas_order_string, "", cas_addrspace_string,
24962529
[hasSM<70>, hasPTX<63>]>;
24972530
defm INT_PTX_ATOM_CAS_#size#_#order#_old#addrspace
24982531
: INT_PTX_ATOM_CAS<"atomic_cmp_swap_i"#size#_#order#_#addrspace, size,
2499-
"", cas_addrspace_string, []>;
2532+
"", "", cas_addrspace_string, []>;
25002533
}
25012534
}
25022535
}
25032536

25042537
// Note that 16-bit CAS support in PTX is emulated.
2505-
defm INT_PTX_ATOM_CAS_G_16 : F_ATOMIC_3<i16, Int16Regs, "", ".global", ".b16", ".cas",
2538+
defm INT_PTX_ATOM_CAS_G_16 : F_ATOMIC_3<i16, Int16Regs, "", "", ".global", ".b16", ".cas",
25062539
atomic_cmp_swap_i16_global, i16imm, [hasSM<70>, hasPTX<63>]>;
2507-
defm INT_PTX_ATOM_CAS_S_16 : F_ATOMIC_3<i16, Int16Regs, "", ".shared", ".b16", ".cas",
2540+
defm INT_PTX_ATOM_CAS_S_16 : F_ATOMIC_3<i16, Int16Regs, "", "", ".shared", ".b16", ".cas",
25082541
atomic_cmp_swap_i16_shared, i16imm, [hasSM<70>, hasPTX<63>]>;
2509-
defm INT_PTX_ATOM_CAS_GEN_16 : F_ATOMIC_3<i16, Int16Regs, "", "", ".b16", ".cas",
2542+
defm INT_PTX_ATOM_CAS_GEN_16 : F_ATOMIC_3<i16, Int16Regs, "", "", "", ".b16", ".cas",
25102543
atomic_cmp_swap_i16_generic, i16imm, [hasSM<70>, hasPTX<63>]>;
25112544

25122545
// Support for scoped atomic operations. Matches

‎llvm/lib/Target/PowerPC/PPCISelLowering.cpp‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -12430,7 +12430,8 @@ static Instruction *callIntrinsic(IRBuilderBase &Builder, Intrinsic::ID Id) {
1243012430
// http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
1243112431
Instruction *PPCTargetLowering::emitLeadingFence(IRBuilderBase &Builder,
1243212432
Instruction *Inst,
12433-
AtomicOrdering Ord) const {
12433+
AtomicOrdering Ord,
12434+
SyncScope::ID SSID) const {
1243412435
if (Ord == AtomicOrdering::SequentiallyConsistent)
1243512436
return callIntrinsic(Builder, Intrinsic::ppc_sync);
1243612437
if (isReleaseOrStronger(Ord))
@@ -12440,7 +12441,8 @@ Instruction *PPCTargetLowering::emitLeadingFence(IRBuilderBase &Builder,
1244012441

1244112442
Instruction *PPCTargetLowering::emitTrailingFence(IRBuilderBase &Builder,
1244212443
Instruction *Inst,
12443-
AtomicOrdering Ord) const {
12444+
AtomicOrdering Ord,
12445+
SyncScope::ID SSID) const {
1244412446
if (Inst->hasAtomicLoad() && isAcquireOrStronger(Ord)) {
1244512447
// See http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html and
1244612448
// http://www.rdrop.com/users/paulmck/scalability/paper/N2745r.2011.03.04a.html

‎llvm/lib/Target/PowerPC/PPCISelLowering.h‎

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -921,10 +921,14 @@ namespace llvm {
921921
return true;
922922
}
923923

924-
Instruction *emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst,
925-
AtomicOrdering Ord) const override;
926-
Instruction *emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst,
927-
AtomicOrdering Ord) const override;
924+
Instruction *
925+
emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst,
926+
AtomicOrdering Ord,
927+
SyncScope::ID SSID = SyncScope::System) const override;
928+
Instruction *
929+
emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst,
930+
AtomicOrdering Ord,
931+
SyncScope::ID SSID = SyncScope::System) const override;
928932

929933
bool shouldInlineQuadwordAtomics() const;
930934

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