Rebase for getMaxNumVectorRegs move

Change-Id: I17c9239229b94c42c35b5683d77f8dfe3f70bafc

Author: jrbyrnes

llvm/lib/Target/AMDGPU/GCNRegPressure.cpp

@@ -100,7 +100,7 @@ bool GCNRegPressure::less(const MachineFunction &MF, const GCNRegPressure &O,
                           unsigned MaxOccupancy) const {
   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
   unsigned ArchVGPRThreshold =
-      ST.getRegisterInfo()->getMaxNumVectorRegs(MF).first;
+      ST.getMaxNumVectorRegs(MF.getFunction()).first;
   unsigned DynamicVGPRBlockSize =
       MF.getInfo<SIMachineFunctionInfo>()->getDynamicVGPRBlockSize();
 
@@ -252,7 +252,7 @@ Printable llvm::print(const GCNRegPressure &RP, const GCNSubtarget *ST,
                       unsigned DynamicVGPRBlockSize,
                       const MachineFunction *MF) {
   unsigned ArchVGPRThreshold =
-      ST->getRegisterInfo()->getMaxNumVectorRegs(*MF).first;
+      ST->getMaxNumVectorRegs(MF->getFunction()).first;
   return Printable(
       [&RP, ST, DynamicVGPRBlockSize, ArchVGPRThreshold, MF](raw_ostream &OS) {
         OS << "VGPRs: " << RP.getArchVGPRNum(ArchVGPRThreshold) << ' '
@@ -906,8 +906,7 @@ bool GCNRegPressurePrinter::runOnMachineFunction(MachineFunction &MF) {
     return Printable([&RP, &MF](raw_ostream &OS) {
       OS << format(PFX "  %-5d", RP.getSGPRNum())
          << format(" %-5d", RP.getVGPRNum(false, MF.getSubtarget<GCNSubtarget>()
-                                                     .getRegisterInfo()
-                                                     ->getMaxNumVectorRegs(MF)
+                                                     .getMaxNumVectorRegs(MF.getFunction())
                                                      .first));
     });
   };

llvm/lib/Target/AMDGPU/GCNRegPressure.h

@@ -132,7 +132,7 @@ struct GCNRegPressure {
         ST.getOccupancyWithNumSGPRs(getSGPRNum()),
         ST.getOccupancyWithNumVGPRs(
             getVGPRNum(ST.hasGFX90AInsts(),
-                       ST.getRegisterInfo()->getMaxNumVectorRegs(MF).first),
+                       ST.getMaxNumVectorRegs(MF.getFunction()).first),
             DynamicVGPRBlockSize));
   }
 

llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp

@@ -191,8 +191,7 @@ static void getRegisterPressures(
     NewPressure = TempUpwardTracker.getPressure();
   }
   unsigned ArchVGPRThreshold = DAG->MF.getSubtarget<GCNSubtarget>()
-                                   .getRegisterInfo()
-                                   ->getMaxNumVectorRegs(DAG->MF)
+                                   .getMaxNumVectorRegs(DAG->MF.getFunction())
                                    .first;
   Pressure[AMDGPU::RegisterPressureSets::SReg_32] = NewPressure.getSGPRNum();
   Pressure[AMDGPU::RegisterPressureSets::VGPR_32] =
@@ -346,8 +345,7 @@ void GCNSchedStrategy::pickNodeFromQueue(SchedBoundary &Zone,
       SGPRPressure = T->getPressure().getSGPRNum();
       VGPRPressure =
           T->getPressure().getArchVGPRNum(DAG->MF.getSubtarget<GCNSubtarget>()
-                                              .getRegisterInfo()
-                                              ->getMaxNumVectorRegs(DAG->MF)
+                                              .getMaxNumVectorRegs(DAG->MF.getFunction())
                                               .first);
     }
   }
@@ -1290,7 +1288,7 @@ void GCNSchedStage::checkScheduling() {
   LLVM_DEBUG(dbgs() << "Region: " << RegionIdx << ".\n");
 
   unsigned ArchVGPRThreshold =
-      ST.getRegisterInfo()->getMaxNumVectorRegs(MF).first;
+      ST.getMaxNumVectorRegs(MF.getFunction()).first;
   if (PressureAfter.getSGPRNum() <= S.SGPRCriticalLimit &&
       PressureAfter.getVGPRNum(ST.hasGFX90AInsts(), ArchVGPRThreshold) <=
           S.VGPRCriticalLimit) {
@@ -1483,7 +1481,7 @@ bool GCNSchedStage::shouldRevertScheduling(unsigned WavesAfter) {
   // For dynamic VGPR mode, we don't want to waste any VGPR blocks.
   if (DAG.MFI.isDynamicVGPREnabled()) {
     unsigned ArchVGPRThreshold =
-        ST.getRegisterInfo()->getMaxNumVectorRegs(MF).first;
+        ST.getMaxNumVectorRegs(MF.getFunction()).first;
     unsigned BlocksBefore = AMDGPU::IsaInfo::getAllocatedNumVGPRBlocks(
         &ST, DAG.MFI.getDynamicVGPRBlockSize(),
         PressureBefore.getVGPRNum(false, ArchVGPRThreshold));

llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp

@@ -211,7 +211,7 @@ bool SIFormMemoryClausesImpl::checkPressure(const MachineInstr &MI,
   if (Occupancy >= MFI->getMinAllowedOccupancy() &&
       MaxPressure.getVGPRNum(
           ST->hasGFX90AInsts(),
-          ST->getRegisterInfo()->getMaxNumVectorRegs(*MI.getMF()).first) <=
+          ST->getMaxNumVectorRegs(MI.getMF()->getFunction()).first) <=
           MaxVGPRs / 2 &&
       MaxPressure.getSGPRNum() <= MaxSGPRs / 2) {
     LastRecordedOccupancy = Occupancy;