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Commit 393dfe4

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Mikhail Gudim
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[RISCV] Remove unnecessary dependencies on vtype register.
1 parent 8ac7210 commit 393dfe4

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4 files changed

+180
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4 files changed

+180
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‎llvm/lib/Target/RISCV/CMakeLists.txt‎

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@@ -67,6 +67,7 @@ add_llvm_target(RISCVCodeGen
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RISCVVectorMaskDAGMutation.cpp
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RISCVVectorPeephole.cpp
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RISCVVLOptimizer.cpp
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RISCVVTypeRegDepMutation.cpp
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RISCVVMV0Elimination.cpp
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RISCVZacasABIFix.cpp
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GISel/RISCVCallLowering.cpp

‎llvm/lib/Target/RISCV/RISCVTargetMachine.cpp‎

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@@ -104,6 +104,11 @@ static cl::opt<bool> EnablePostMISchedLoadStoreClustering(
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cl::desc("Enable PostRA load and store clustering in the machine scheduler"),
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cl::init(true));
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static cl::opt<bool> EnableVTypeRegDepMutation(
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"riscv-postmisched-vtype-reg-dep-mutation", cl::Hidden,
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cl::desc("Remove unnecessary dependencies on vtype register"),
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cl::init(false));
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static cl::opt<bool>
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EnableVLOptimizer("riscv-enable-vl-optimizer",
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cl::desc("Enable the RISC-V VL Optimizer pass"),
@@ -323,6 +328,8 @@ RISCVTargetMachine::createPostMachineScheduler(MachineSchedContext *C) const {
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DAG->addMutation(createStoreClusterDAGMutation(
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DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
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}
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if (EnableVTypeRegDepMutation)
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DAG->addMutation(createRISCVVTypeRegDepMutation(DAG->TRI));
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return DAG;
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}

‎llvm/lib/Target/RISCV/RISCVTargetMachine.h‎

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@@ -68,6 +68,8 @@ class RISCVTargetMachine : public CodeGenTargetMachineImpl {
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std::unique_ptr<ScheduleDAGMutation>
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createRISCVVectorMaskDAGMutation(const TargetRegisterInfo *TRI);
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std::unique_ptr<ScheduleDAGMutation>
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createRISCVVTypeRegDepMutation(const TargetRegisterInfo *TRI);
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} // namespace llvm
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#endif

‎llvm/lib/Target/RISCV/RISCVVTypeRegDepMutation.cpp‎

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@@ -0,0 +1,170 @@
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//===- RISCVVTypeRegDepMutation.cpp - RISC-V Vector Mask DAGMutation ----===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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#include "MCTargetDesc/RISCVBaseInfo.h"
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#include "MCTargetDesc/RISCVMCTargetDesc.h"
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#include "RISCVRegisterInfo.h"
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#include "RISCVTargetMachine.h"
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#include "llvm/CodeGen/LiveIntervals.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/ScheduleDAGInstrs.h"
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#include "llvm/CodeGen/ScheduleDAGMutation.h"
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#include "llvm/TargetParser/RISCVTargetParser.h"
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#define DEBUG_TYPE "machine-scheduler"
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namespace llvm {
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static void collectPossibleVSetsForMI(
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MachineInstr *MI, int RequiredVL, unsigned PossibleVType,
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SmallVector<std::tuple<MachineInstr *, int>> &VSetInstrVLs,
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SmallVector<MachineInstr *> &PossibleVSets) {
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unsigned VTypeMask = unsigned(-1);
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if (MI->getOpcode() == RISCV::PseudoVLE8_V_MF4 ||
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MI->getOpcode() == RISCV::PseudoVLE8_V_MF8) {
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// TODO: actually, we care about the ratio lmul / sew
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VTypeMask = ~((0x7 << 3) | 0x7);
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}
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unsigned RequiredMaskedVType = PossibleVType & VTypeMask;
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for (auto &VSetInstrVL : VSetInstrVLs) {
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MachineInstr *VSetInstr = std::get<0>(VSetInstrVL);
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if ((std::get<1>(VSetInstrVL) == RequiredVL) &&
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((VSetInstr->getOperand(2).getImm() & VTypeMask) ==
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RequiredMaskedVType)) {
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PossibleVSets.push_back(VSetInstr);
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}
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}
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return;
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}
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class RISCVVTypeRegDepMutation : public ScheduleDAGMutation {
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private:
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const TargetRegisterInfo *TRI;
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public:
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RISCVVTypeRegDepMutation(const TargetRegisterInfo *TRI) : TRI(TRI) {}
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void apply(ScheduleDAGInstrs *DAG) override;
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};
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// For each instruction I that reads vtype register:
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// (1) compute reaching definitions of vtype register.
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// (2) From all vtype reg definitions in the basic block collect the ones
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// compatible with those found in (1) (call this set Comp(I)).
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// (3) for each instruction vset in Comp(I) if there is data dependence on
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// vtype reg vset->I, remove it, also, remove all anti-depencies I->vset (4)
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// Choose by some heuristic an instruction best_vset from Comp(I) and insert
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// data dependence on vtype: best_vset->I. NOTE: code below is not correct,
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// but by luck it doesn't cause any issues on SPEC.
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void RISCVVTypeRegDepMutation::apply(ScheduleDAGInstrs *DAG) {
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SmallVector<std::tuple<MachineInstr *, int>> VSetInstrVLs;
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SmallVector<std::tuple<MachineInstr *, int, MachineInstr *>> MIVLVSetInstrs;
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int CurrentVL = -1;
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for (auto MBBI = DAG->begin(); MBBI != DAG->end(); ++MBBI) {
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switch (MBBI->getOpcode()) {
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default:
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continue;
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case RISCV::PseudoVSETIVLI: {
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CurrentVL = MBBI->getOperand(1).getImm();
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VSetInstrVLs.push_back({&*MBBI, CurrentVL});
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continue;
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}
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case RISCV::PseudoVSETVLI: {
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continue;
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}
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case RISCV::PseudoVSETVLIX0X0: {
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// TODO: the case when we're setting to VLMax
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// if (MBBI->getOperand(0).getReg() != RISCV::X0) {
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// continue;
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// }
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VSetInstrVLs.push_back(std::make_pair(&*MBBI, CurrentVL));
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continue;
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}
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case RISCV::PseudoVLE8_V_MF8:
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case RISCV::PseudoVLE8_V_MF4: {
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if (!VSetInstrVLs.empty())
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MIVLVSetInstrs.push_back(
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{&*MBBI, CurrentVL, std::get<0>(VSetInstrVLs.back())});
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continue;
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}
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}
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}
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DenseMap<MachineInstr *,
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std::tuple<SmallVector<MachineInstr *>, MachineInstr *>>
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MIToPossibleVSetsMap;
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for (auto &MIVLVSetInstr : MIVLVSetInstrs) {
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MachineInstr *OrigVSetInstr = std::get<2>(MIVLVSetInstr);
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int RequiredVL = std::get<1>(MIVLVSetInstr);
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int PossibleVType = OrigVSetInstr->getOperand(2).getImm();
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SmallVector<MachineInstr *> PossibleVSets;
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MachineInstr *MI = std::get<0>(MIVLVSetInstr);
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collectPossibleVSetsForMI(MI, RequiredVL, PossibleVType, VSetInstrVLs,
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PossibleVSets);
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MIToPossibleVSetsMap[MI] = {PossibleVSets, OrigVSetInstr};
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}
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DenseMap<MachineInstr *, SUnit *> VSetToSUMap;
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for (SUnit &SU : DAG->SUnits) {
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if (!SU.isInstr())
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continue;
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MachineInstr *MI = SU.getInstr();
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unsigned Opc = MI->getOpcode();
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if ((Opc == RISCV::PseudoVSETIVLI) || (Opc == RISCV::PseudoVSETVLI) ||
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(Opc == RISCV::PseudoVSETVLIX0))
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VSetToSUMap[MI] = &SU;
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}
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for (SUnit &SU : DAG->SUnits) {
123+
if (!SU.isInstr())
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continue;
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MachineInstr *MI = SU.getInstr();
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SmallVector<MachineInstr *> &PossibleVSets =
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std::get<0>(MIToPossibleVSetsMap[MI]);
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if (PossibleVSets.size() < 2)
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continue;
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// Choose the earliest (in the original program order) VSET insruction
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// satisfying the vtype requirements of MI.
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SUnit *NewVSetSU = VSetToSUMap[PossibleVSets[0]];
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SUnit *OldVSetSU = VSetToSUMap[std::get<1>(MIToPossibleVSetsMap[MI])];
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for (auto &D : SU.Succs) {
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if (D.getKind() != SDep::Kind::Anti)
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continue;
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unsigned Reg = D.getReg();
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if (Reg != RISCV::VL && Reg != RISCV::VTYPE)
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continue;
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SUnit &AntiDepSucc = *D.getSUnit();
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// TODO: we can only remove anti-depence to compatible vsets.
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for (auto &P : AntiDepSucc.Preds) {
143+
if (P.getSUnit() == &SU) {
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AntiDepSucc.removePred(P);
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}
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}
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}
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for (auto &D : SU.Preds) {
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if (D.getSUnit() != OldVSetSU)
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continue;
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if (D.getKind() != SDep::Kind::Data)
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continue;
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unsigned Reg = D.getReg();
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if (Reg != RISCV::VL && Reg != RISCV::VTYPE)
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continue;
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unsigned Latency = D.getLatency();
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SU.removePred(D);
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SDep NewSDep(NewVSetSU, SDep::Kind::Data, Reg);
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NewSDep.setLatency(Latency);
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SU.addPred(NewSDep);
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}
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}
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return;
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}
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std::unique_ptr<ScheduleDAGMutation>
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createRISCVVTypeRegDepMutation(const TargetRegisterInfo *TRI) {
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return std::make_unique<RISCVVTypeRegDepMutation>(TRI);
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}
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} // namespace llvm

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