We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
1 parent 7efdd4f commit 394f1dbCopy full SHA for 394f1db
llvm/include/llvm/CodeGen/ModuloSchedule.h
@@ -60,7 +60,6 @@
60
#ifndef LLVM_CODEGEN_MODULOSCHEDULE_H
61
#define LLVM_CODEGEN_MODULOSCHEDULE_H
62
63
-#include "llvm/ADT/SmallSet.h"
64
#include "llvm/CodeGen/MachineFunction.h"
65
#include "llvm/CodeGen/MachineLoopUtils.h"
66
#include "llvm/CodeGen/TargetInstrInfo.h"
llvm/test/CodeGen/AArch64/aarch64-swp-ws-live-intervals.mir
@@ -1,5 +1,5 @@
1
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
2
-# RUN: llc --mtriple=aarch64 %s -O2 -run-pass=pipeliner -o - | FileCheck %s
+# RUN: llc --mtriple=aarch64 %s -run-pass=pipeliner -o - | FileCheck %s
3
4
...
5
---
0 commit comments