[AArch64][NFC] Add test for vector sdiv scalarization

Author: SavchenkoValeriy

llvm/test/CodeGen/AArch64/sdiv-by-const-promoted-ops.ll

@@ -0,0 +1,141 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s
+
+define <8 x i16> @sdiv_v8i16_by_7(<8 x i16> %x) {
+; CHECK-LABEL: sdiv_v8i16_by_7:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #18725 // =0x4925
+; CHECK-NEXT:    dup v1.8h, w8
+; CHECK-NEXT:    smull2 v2.4s, v0.8h, v1.8h
+; CHECK-NEXT:    smull v0.4s, v0.4h, v1.4h
+; CHECK-NEXT:    uzp2 v0.8h, v0.8h, v2.8h
+; CHECK-NEXT:    sshr v0.8h, v0.8h, #1
+; CHECK-NEXT:    usra v0.8h, v0.8h, #15
+; CHECK-NEXT:    ret
+  %div = sdiv <8 x i16> %x, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
+  ret <8 x i16> %div
+}
+
+define <16 x i16> @sdiv_v16i16_by_7(<16 x i16> %x) {
+; CHECK-LABEL: sdiv_v16i16_by_7:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    smov x11, v0.h[1]
+; CHECK-NEXT:    smov x10, v0.h[0]
+; CHECK-NEXT:    mov x8, #-56173 // =0xffffffffffff2493
+; CHECK-NEXT:    smov x13, v0.h[3]
+; CHECK-NEXT:    smov x14, v1.h[1]
+; CHECK-NEXT:    movk x8, #37449, lsl #16
+; CHECK-NEXT:    smov x16, v1.h[0]
+; CHECK-NEXT:    smov w12, v0.h[1]
+; CHECK-NEXT:    smov w15, v0.h[0]
+; CHECK-NEXT:    smov x18, v1.h[2]
+; CHECK-NEXT:    smov w0, v0.h[3]
+; CHECK-NEXT:    smov w1, v1.h[1]
+; CHECK-NEXT:    smull x11, w11, w8
+; CHECK-NEXT:    smov w2, v1.h[0]
+; CHECK-NEXT:    smov x9, v0.h[2]
+; CHECK-NEXT:    smull x10, w10, w8
+; CHECK-NEXT:    smov w17, v0.h[2]
+; CHECK-NEXT:    smov w3, v1.h[2]
+; CHECK-NEXT:    smull x13, w13, w8
+; CHECK-NEXT:    smull x14, w14, w8
+; CHECK-NEXT:    add x12, x12, x11, lsr #32
+; CHECK-NEXT:    smull x16, w16, w8
+; CHECK-NEXT:    add x10, x15, x10, lsr #32
+; CHECK-NEXT:    smull x15, w18, w8
+; CHECK-NEXT:    add x11, x0, x13, lsr #32
+; CHECK-NEXT:    smov x0, v0.h[4]
+; CHECK-NEXT:    add x13, x1, x14, lsr #32
+; CHECK-NEXT:    asr w18, w10, #2
+; CHECK-NEXT:    smull x9, w9, w8
+; CHECK-NEXT:    add x14, x2, x16, lsr #32
+; CHECK-NEXT:    asr w16, w12, #2
+; CHECK-NEXT:    smov x2, v1.h[3]
+; CHECK-NEXT:    add w18, w18, w10, lsr #31
+; CHECK-NEXT:    add x15, x3, x15, lsr #32
+; CHECK-NEXT:    smov w10, v0.h[5]
+; CHECK-NEXT:    add w12, w16, w12, lsr #31
+; CHECK-NEXT:    asr w16, w14, #2
+; CHECK-NEXT:    add x9, x17, x9, lsr #32
+; CHECK-NEXT:    fmov s2, w18
+; CHECK-NEXT:    smov w17, v0.h[4]
+; CHECK-NEXT:    smull x0, w0, w8
+; CHECK-NEXT:    add w14, w16, w14, lsr #31
+; CHECK-NEXT:    asr w16, w13, #2
+; CHECK-NEXT:    asr w1, w9, #2
+; CHECK-NEXT:    smov x18, v0.h[5]
+; CHECK-NEXT:    fmov s3, w14
+; CHECK-NEXT:    mov v2.h[1], w12
+; CHECK-NEXT:    add w12, w16, w13, lsr #31
+; CHECK-NEXT:    smov w13, v1.h[3]
+; CHECK-NEXT:    smov x14, v1.h[4]
+; CHECK-NEXT:    smull x16, w2, w8
+; CHECK-NEXT:    add w1, w1, w9, lsr #31
+; CHECK-NEXT:    add x17, x17, x0, lsr #32
+; CHECK-NEXT:    asr w0, w15, #2
+; CHECK-NEXT:    mov v3.h[1], w12
+; CHECK-NEXT:    smov w12, v1.h[4]
+; CHECK-NEXT:    smull x18, w18, w8
+; CHECK-NEXT:    mov v2.h[2], w1
+; CHECK-NEXT:    asr w1, w11, #2
+; CHECK-NEXT:    add w15, w0, w15, lsr #31
+; CHECK-NEXT:    add x13, x13, x16, lsr #32
+; CHECK-NEXT:    smov x16, v1.h[5]
+; CHECK-NEXT:    smull x14, w14, w8
+; CHECK-NEXT:    add w11, w1, w11, lsr #31
+; CHECK-NEXT:    smov x0, v0.h[6]
+; CHECK-NEXT:    add x10, x10, x18, lsr #32
+; CHECK-NEXT:    asr w1, w13, #2
+; CHECK-NEXT:    mov v3.h[2], w15
+; CHECK-NEXT:    smov w15, v1.h[5]
+; CHECK-NEXT:    add x12, x12, x14, lsr #32
+; CHECK-NEXT:    mov v2.h[3], w11
+; CHECK-NEXT:    asr w11, w17, #2
+; CHECK-NEXT:    add w13, w1, w13, lsr #31
+; CHECK-NEXT:    smull x16, w16, w8
+; CHECK-NEXT:    smov x14, v1.h[6]
+; CHECK-NEXT:    asr w18, w12, #2
+; CHECK-NEXT:    add w11, w11, w17, lsr #31
+; CHECK-NEXT:    smov w9, v0.h[6]
+; CHECK-NEXT:    mov v3.h[3], w13
+; CHECK-NEXT:    smull x17, w0, w8
+; CHECK-NEXT:    smov x0, v1.h[7]
+; CHECK-NEXT:    add x13, x15, x16, lsr #32
+; CHECK-NEXT:    add w12, w18, w12, lsr #31
+; CHECK-NEXT:    smov w16, v1.h[6]
+; CHECK-NEXT:    mov v2.h[4], w11
+; CHECK-NEXT:    smov x11, v0.h[7]
+; CHECK-NEXT:    smull x14, w14, w8
+; CHECK-NEXT:    asr w15, w10, #2
+; CHECK-NEXT:    asr w18, w13, #2
+; CHECK-NEXT:    smov w1, v0.h[7]
+; CHECK-NEXT:    mov v3.h[4], w12
+; CHECK-NEXT:    add x9, x9, x17, lsr #32
+; CHECK-NEXT:    add w10, w15, w10, lsr #31
+; CHECK-NEXT:    add w12, w18, w13, lsr #31
+; CHECK-NEXT:    add x13, x16, x14, lsr #32
+; CHECK-NEXT:    smov w14, v1.h[7]
+; CHECK-NEXT:    smull x11, w11, w8
+; CHECK-NEXT:    smull x8, w0, w8
+; CHECK-NEXT:    mov v2.h[5], w10
+; CHECK-NEXT:    asr w10, w9, #2
+; CHECK-NEXT:    mov v3.h[5], w12
+; CHECK-NEXT:    asr w12, w13, #2
+; CHECK-NEXT:    add w9, w10, w9, lsr #31
+; CHECK-NEXT:    add x10, x1, x11, lsr #32
+; CHECK-NEXT:    add w11, w12, w13, lsr #31
+; CHECK-NEXT:    add x8, x14, x8, lsr #32
+; CHECK-NEXT:    mov v2.h[6], w9
+; CHECK-NEXT:    asr w9, w10, #2
+; CHECK-NEXT:    mov v3.h[6], w11
+; CHECK-NEXT:    asr w11, w8, #2
+; CHECK-NEXT:    add w9, w9, w10, lsr #31
+; CHECK-NEXT:    add w8, w11, w8, lsr #31
+; CHECK-NEXT:    mov v2.h[7], w9
+; CHECK-NEXT:    mov v3.h[7], w8
+; CHECK-NEXT:    mov v0.16b, v2.16b
+; CHECK-NEXT:    mov v1.16b, v3.16b
+; CHECK-NEXT:    ret
+  %div = sdiv <16 x i16> %x, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
+  ret <16 x i16> %div
+}