Remove shared opcode & subsequent changes

Author: HolyMolyCowMan

llvm/docs/GlobalISel/GenericOpcode.rst

@@ -536,12 +536,6 @@ G_FPTRUNC
 
 Convert a floating point value to a narrower type.
 
-G_FPTRUNC_ODD
-^^^^^^^^^^^^^
-
-Convert a floating point value to a narrower type using round-to-odd rounding 
-mode.
-
 G_FPTOSI, G_FPTOUI, G_SITOFP, G_UITOFP
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 

llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h

@@ -1332,21 +1332,6 @@ class LLVM_ABI MachineIRBuilder {
   buildFPTrunc(const DstOp &Res, const SrcOp &Op,
                std::optional<unsigned> Flags = std::nullopt);
 
-  /// Build and insert \p Res = G_FPTRUNC_ODD \p Op
-  ///
-  /// G_FPTRUNC_ODD converts a floating-point value into one with a smaller type
-  /// using round to odd.
-  ///
-  /// \pre setBasicBlock or setMI must have been called.
-  /// \pre \p Res must be a generic virtual register with scalar or vector type.
-  /// \pre \p Op must be a generic virtual register with scalar or vector type.
-  /// \pre \p Res must be smaller than \p Op
-  ///
-  /// \return The newly created instruction.
-  MachineInstrBuilder
-  buildFPTruncOdd(const DstOp &Res, const SrcOp &Op,
-                  std::optional<unsigned> Flags = std::nullopt);
-
   /// Build and insert \p Res = G_TRUNC \p Op
   ///
   /// G_TRUNC extracts the low bits of a type. For a vector type each element is

llvm/include/llvm/Support/TargetOpcodes.def

@@ -692,9 +692,6 @@ HANDLE_TARGET_OPCODE(G_FPEXT)
 /// Generic float to signed-int conversion
 HANDLE_TARGET_OPCODE(G_FPTRUNC)
 
-/// Generic float to signed-int conversion using round to odd
-HANDLE_TARGET_OPCODE(G_FPTRUNC_ODD)
-
 /// Generic float to signed-int conversion
 HANDLE_TARGET_OPCODE(G_FPTOSI)
 

llvm/include/llvm/Target/GenericOpcodes.td

@@ -782,12 +782,6 @@ def G_FPTRUNC : GenericInstruction {
   let hasSideEffects = false;
 }
 
-def G_FPTRUNC_ODD : GenericInstruction {
-  let OutOperandList = (outs type0:$dst);
-  let InOperandList = (ins type1:$src);
-  let hasSideEffects = false;
-}
-
 def G_FPTOSI : GenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins type1:$src);

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

@@ -5595,7 +5595,6 @@ LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
   case G_ANYEXT:
   case G_FPEXT:
   case G_FPTRUNC:
-  case G_FPTRUNC_ODD:
   case G_SITOFP:
   case G_UITOFP:
   case G_FPTOSI:
@@ -8477,8 +8476,7 @@ LegalizerHelper::lowerFPTOINT_SAT(MachineInstr &MI) {
   return Legalized;
 }
 
-// f64 -> f16 conversion using round-to-nearest-even rounding mode for scalars
-// and round-to-odd for vectors.
+// f64 -> f16 conversion using round-to-nearest-even rounding mode.
 LegalizerHelper::LegalizeResult
 LegalizerHelper::lowerFPTRUNC_F64_TO_F16(MachineInstr &MI) {
   const LLT S1 = LLT::scalar(1);
@@ -8488,28 +8486,8 @@ LegalizerHelper::lowerFPTRUNC_F64_TO_F16(MachineInstr &MI) {
   assert(MRI.getType(Dst).getScalarType() == LLT::scalar(16) &&
          MRI.getType(Src).getScalarType() == LLT::scalar(64));
 
-  if (MRI.getType(Src).isVector()) {
-    LLT SrcTy = MRI.getType(Src);
-
-    LLT MidTy = LLT::fixed_vector(SrcTy.getNumElements(), LLT::scalar(32));
-
-    // Check if G_FPTRUNC_ODD has been added to the legalizer and the resultant
-    // types can be legalized.
-    auto LegalizeAction =
-        LI.getAction({TargetOpcode::G_FPTRUNC_ODD, {MidTy, SrcTy}}).Action;
-
-    if (LegalizeAction == LegalizeActions::Unsupported ||
-        LegalizeAction == LegalizeActions::NotFound)
-      return UnableToLegalize;
-
-    MIRBuilder.setInstrAndDebugLoc(MI);
-
-    MachineInstrBuilder Mid = MIRBuilder.buildFPTruncOdd(MidTy, Src);
-    MIRBuilder.buildFPTrunc(Dst, Mid.getReg(0));
-
-    MI.eraseFromParent();
-    return Legalized;
-  }
+  if (MRI.getType(Src).isVector())
+    return UnableToLegalize;
 
   if (MI.getFlag(MachineInstr::FmAfn)) {
     unsigned Flags = MI.getFlags();

llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp

@@ -936,12 +936,6 @@ MachineIRBuilder::buildFPTrunc(const DstOp &Res, const SrcOp &Op,
   return buildInstr(TargetOpcode::G_FPTRUNC, Res, Op, Flags);
 }
 
-MachineInstrBuilder
-MachineIRBuilder::buildFPTruncOdd(const DstOp &Res, const SrcOp &Op,
-                                  std::optional<unsigned> Flags) {
-  return buildInstr(TargetOpcode::G_FPTRUNC_ODD, Res, Op, Flags);
-}
-
 MachineInstrBuilder MachineIRBuilder::buildICmp(CmpInst::Predicate Pred,
                                                 const DstOp &Res,
                                                 const SrcOp &Op0,

llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

@@ -831,11 +831,6 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
       .clampNumElements(1, v2s64, v2s64)
       .scalarize(0);
 
-  getActionDefinitionsBuilder(G_FPTRUNC_ODD)
-      .legalFor({{s16, s32}, {s32, s64}, {v4s16, v4s32}, {v2s32, v2s64}})
-      .clampMaxNumElements(1, s32, 4)
-      .clampMaxNumElements(1, s64, 2);
-
   getActionDefinitionsBuilder(G_FPEXT)
       .legalFor(
           {{s32, s16}, {s64, s16}, {s64, s32}, {v4s32, v4s16}, {v2s64, v2s32}})

llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir

@@ -560,9 +560,6 @@
 # DEBUG-NEXT: G_FPTRUNC (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
 # DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
-# DEBUG-NEXT: G_FPTRUNC_ODD (opcode 204): 2 type indices, 0 imm indices
-# DEBUG-NEXT: .. the first uncovered type index: 2, OK 
-# DEBUG-NEXT: .. the first uncovered imm index: 0, OK 
 # DEBUG-NEXT: G_FPTOSI (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
 # DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected

llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt

@@ -423,7 +423,6 @@ Key: G_FPTOSI_SAT:  [ 0.00  0.00 ]
 Key: G_FPTOUI:  [ 0.00  0.00 ]
 Key: G_FPTOUI_SAT:  [ 0.00  0.00 ]
 Key: G_FPTRUNC:  [ 0.00  0.00 ]
-Key: G_FPTRUNC_ODD:  [ 0.00  0.00 ]
 Key: G_FRAME_INDEX:  [ 0.00  0.00 ]
 Key: G_FREEZE:  [ 0.00  0.00 ]
 Key: G_FREM:  [ 0.00  0.00 ]

llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt

@@ -423,7 +423,6 @@ Key: G_FPTOSI_SAT:  [ 0.00  0.00 ]
 Key: G_FPTOUI:  [ 0.00  0.00 ]
 Key: G_FPTOUI_SAT:  [ 0.00  0.00 ]
 Key: G_FPTRUNC:  [ 0.00  0.00 ]
-Key: G_FPTRUNC_ODD:  [ 0.00  0.00 ]
 Key: G_FRAME_INDEX:  [ 0.00  0.00 ]
 Key: G_FREEZE:  [ 0.00  0.00 ]
 Key: G_FREM:  [ 0.00  0.00 ]