@@ -147,54 +147,6 @@ InsertPointAnalysis::getLastInsertPointIter(const LiveInterval &CurLI,
147147 return LIS.getInstructionFromIndex (LIP);
148148}
149149
150- bool InsertPointAnalysis::canSplitBeforeProlog (const LiveInterval &CurLI,
151- const MachineBasicBlock &MBB) {
152- const TargetInstrInfo *TII = MBB.getParent ()->getSubtarget ().getInstrInfo ();
153-
154- for (auto &MI : MBB) {
155- if (MI.isPHI () || MI.isPosition () || MI.isDebugInstr () ||
156- MI.isPseudoProbe ())
157- continue ;
158-
159- if (!TII->isBasicBlockPrologue (MI))
160- return true ;
161-
162- for (auto &MO : MI.operands ()) {
163- if (!MO.isReg () || !MO.isDef () || !MO.getReg ().isVirtual ())
164- continue ;
165-
166- // For the AMDGPU target if a MBB contains exec mask restore preamble,
167- // SplitEditor may get state when it cannot insert a spill instruction
168- // at the begin of the MBB.
169- // E.g. for a MIR
170- // bb.100:
171- // %1 = S_OR_SAVEEXEC_B64 %2, implicit-def $exec, implicit-def $scc,
172- // implicit $exec
173- // ...
174- // use %1
175- // If the regalloc try to allocate a virtreg to the physreg already
176- // assigned to virtreg %1 and the pyhsreg is computed as the best
177- // candidate for split, it may insert COPY instruction.
178- // bb.100:
179- // %1 = S_OR_SAVEEXEC_B64 %2, implicit-def $exec, implicit-def $scc,
180- // implicit $exec
181- // %2 = COPY %orig
182- // ...
183- // use %1
184- // Thus %1 and %orig still have interference. We may add cost for the
185- // physreg candidate or abandon the candidate.
186- const MachineRegisterInfo &MRI = MBB.getParent ()->getRegInfo ();
187- const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo ();
188- const TargetRegisterClass *RC = MRI.getRegClass (MO.getReg ());
189- const TargetRegisterClass *CurRC = MRI.getRegClass (CurLI.reg ());
190- if (TRI->getCommonSubClass (RC, CurRC))
191- return false ;
192- }
193- }
194-
195- return true ;
196- }
197-
198150// ===----------------------------------------------------------------------===//
199151// Split Analysis
200152// ===----------------------------------------------------------------------===//
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