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jwanggit86jwanggit86
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Make printer print INV2PI instead of of literal numbers to support
assembler-disassembler round-trip.
1 parent 2c19357 commit 3a3ef24

30 files changed

+187
-187
lines changed

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -524,7 +524,7 @@ static bool printImmediateFP16(uint32_t Imm, const MCSubtargetInfo &STI,
524524
else if (Imm == 0xC400)
525525
O << "-4.0";
526526
else if (Imm == 0x3118 && STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm))
527-
O << "0.15915494";
527+
O << "INV2PI";
528528
else
529529
return false;
530530

@@ -550,7 +550,7 @@ static bool printImmediateBFloat16(uint32_t Imm, const MCSubtargetInfo &STI,
550550
else if (Imm == 0xC080)
551551
O << "-4.0";
552552
else if (Imm == 0x3E22 && STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm))
553-
O << "0.15915494";
553+
O << "INV2PI";
554554
else
555555
return false;
556556

@@ -648,7 +648,7 @@ bool AMDGPUInstPrinter::printImmediateFloat32(uint32_t Imm,
648648
O << "-4.0";
649649
else if (Imm == 0x3e22f983 &&
650650
STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm))
651-
O << "0.15915494";
651+
O << "INV2PI";
652652
else
653653
return false;
654654

@@ -699,7 +699,7 @@ void AMDGPUInstPrinter::printImmediate64(uint64_t Imm,
699699
O << "-4.0";
700700
else if (Imm == 0x3fc45f306dc9c882 &&
701701
STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm))
702-
O << "0.15915494309189532";
702+
O << "INV2PI";
703703
else
704704
printLiteral64(Imm, O, IsFP);
705705
}

‎llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.writelane.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -112,12 +112,12 @@ define amdgpu_ps float @test_writelane_imminv2pi_s_v(i32 inreg %lane, i32 %vdst.
112112
;
113113
; GFX8-LABEL: test_writelane_imminv2pi_s_v:
114114
; GFX8: ; %bb.0:
115-
; GFX8-NEXT: v_writelane_b32 v0, 0.15915494, s2
115+
; GFX8-NEXT: v_writelane_b32 v0, INV2PI, s2
116116
; GFX8-NEXT: ; return to shader part epilog
117117
;
118118
; GFX10-LABEL: test_writelane_imminv2pi_s_v:
119119
; GFX10: ; %bb.0:
120-
; GFX10-NEXT: v_writelane_b32 v0, 0.15915494, s2
120+
; GFX10-NEXT: v_writelane_b32 v0, INV2PI, s2
121121
; GFX10-NEXT: ; return to shader part epilog
122122
%writelane = call i32 @llvm.amdgcn.writelane(i32 bitcast (float 0x3FC45F3060000000 to i32), i32 %lane, i32 %vdst.in)
123123
%writelane.cast = bitcast i32 %writelane to float

‎llvm/test/CodeGen/AMDGPU/bitreverse-inline-immediates.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -364,7 +364,7 @@ define void @materialize_not_neg4.0_i32(ptr addrspace(1) %out) {
364364

365365
; GCN-LABEL: {{^}}materialize_not_inv2pi_i32:
366366
; SI: v_mov_b32_e32 v{{[0-9]+}}, 0xc1dd067c
367-
; VI: v_not_b32_e32 v{{[0-9]+}}, 0.15915494
367+
; VI: v_not_b32_e32 v{{[0-9]+}}, INV2PI
368368
define void @materialize_not_inv2pi_i32(ptr addrspace(1) %out) {
369369
store i32 -1042479492, ptr addrspace(1) %out
370370
ret void

‎llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1470,7 +1470,7 @@ define half @v_fneg_inv2pi_minnum_f16(half %a) #0 {
14701470
; VI: ; %bb.0:
14711471
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
14721472
; VI-NEXT: v_max_f16_e32 v0, v0, v0
1473-
; VI-NEXT: v_min_f16_e32 v0, 0.15915494, v0
1473+
; VI-NEXT: v_min_f16_e32 v0, INV2PI, v0
14741474
; VI-NEXT: v_xor_b32_e32 v0, 0x8000, v0
14751475
; VI-NEXT: s_setpc_b64 s[30:31]
14761476
;
@@ -1479,23 +1479,23 @@ define half @v_fneg_inv2pi_minnum_f16(half %a) #0 {
14791479
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
14801480
; GFX11-NEXT: v_max_f16_e32 v0, v0, v0
14811481
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
1482-
; GFX11-NEXT: v_min_f16_e32 v0, 0.15915494, v0
1482+
; GFX11-NEXT: v_min_f16_e32 v0, INV2PI, v0
14831483
; GFX11-NEXT: v_xor_b32_e32 v0, 0x8000, v0
14841484
; GFX11-NEXT: s_setpc_b64 s[30:31]
14851485
; GFX11-SAFE-TRUE16-LABEL: v_fneg_inv2pi_minnum_f16:
14861486
; GFX11-SAFE-TRUE16: ; %bb.0:
14871487
; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
14881488
; GFX11-SAFE-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
14891489
; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
1490-
; GFX11-SAFE-TRUE16-NEXT: v_min_f16_e32 v0.l, 0.15915494, v0.l
1490+
; GFX11-SAFE-TRUE16-NEXT: v_min_f16_e32 v0.l, INV2PI, v0.l
14911491
; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
14921492
; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
14931493
; GFX11-NSZ-TRUE16-LABEL: v_fneg_inv2pi_minnum_f16:
14941494
; GFX11-NSZ-TRUE16: ; %bb.0:
14951495
; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
14961496
; GFX11-NSZ-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
14971497
; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
1498-
; GFX11-NSZ-TRUE16-NEXT: v_min_f16_e32 v0.l, 0.15915494, v0.l
1498+
; GFX11-NSZ-TRUE16-NEXT: v_min_f16_e32 v0.l, INV2PI, v0.l
14991499
; GFX11-NSZ-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
15001500
; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
15011501
%min = call half @llvm.minnum.f16(half 0xH3118, half %a)
@@ -1516,7 +1516,7 @@ define half @v_fneg_neg_inv2pi_minnum_f16(half %a) #0 {
15161516
; VI: ; %bb.0:
15171517
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
15181518
; VI-NEXT: v_max_f16_e32 v0, v0, v0
1519-
; VI-NEXT: v_min_f16_e32 v0, 0.15915494, v0
1519+
; VI-NEXT: v_min_f16_e32 v0, INV2PI, v0
15201520
; VI-NEXT: v_xor_b32_e32 v0, 0x8000, v0
15211521
; VI-NEXT: s_setpc_b64 s[30:31]
15221522
;
@@ -1525,23 +1525,23 @@ define half @v_fneg_neg_inv2pi_minnum_f16(half %a) #0 {
15251525
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
15261526
; GFX11-NEXT: v_max_f16_e32 v0, v0, v0
15271527
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
1528-
; GFX11-NEXT: v_min_f16_e32 v0, 0.15915494, v0
1528+
; GFX11-NEXT: v_min_f16_e32 v0, INV2PI, v0
15291529
; GFX11-NEXT: v_xor_b32_e32 v0, 0x8000, v0
15301530
; GFX11-NEXT: s_setpc_b64 s[30:31]
15311531
; GFX11-SAFE-TRUE16-LABEL: v_fneg_neg_inv2pi_minnum_f16:
15321532
; GFX11-SAFE-TRUE16: ; %bb.0:
15331533
; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
15341534
; GFX11-SAFE-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
15351535
; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
1536-
; GFX11-SAFE-TRUE16-NEXT: v_min_f16_e32 v0.l, 0.15915494, v0.l
1536+
; GFX11-SAFE-TRUE16-NEXT: v_min_f16_e32 v0.l, INV2PI, v0.l
15371537
; GFX11-SAFE-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
15381538
; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
15391539
; GFX11-NSZ-TRUE16-LABEL: v_fneg_neg_inv2pi_minnum_f16:
15401540
; GFX11-NSZ-TRUE16: ; %bb.0:
15411541
; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
15421542
; GFX11-NSZ-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
15431543
; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
1544-
; GFX11-NSZ-TRUE16-NEXT: v_min_f16_e32 v0.l, 0.15915494, v0.l
1544+
; GFX11-NSZ-TRUE16-NEXT: v_min_f16_e32 v0.l, INV2PI, v0.l
15451545
; GFX11-NSZ-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
15461546
; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
15471547
%min = call half @llvm.minnum.f16(half 0xH3118, half %a)
@@ -1650,7 +1650,7 @@ define half @v_fneg_inv2pi_minnum_foldable_use_f16(half %a, half %b) #0 {
16501650
; VI: ; %bb.0:
16511651
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
16521652
; VI-NEXT: v_max_f16_e32 v0, v0, v0
1653-
; VI-NEXT: v_min_f16_e32 v0, 0.15915494, v0
1653+
; VI-NEXT: v_min_f16_e32 v0, INV2PI, v0
16541654
; VI-NEXT: v_mul_f16_e64 v0, -v0, v1
16551655
; VI-NEXT: s_setpc_b64 s[30:31]
16561656
;
@@ -1659,23 +1659,23 @@ define half @v_fneg_inv2pi_minnum_foldable_use_f16(half %a, half %b) #0 {
16591659
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
16601660
; GFX11-NEXT: v_max_f16_e32 v0, v0, v0
16611661
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
1662-
; GFX11-NEXT: v_min_f16_e32 v0, 0.15915494, v0
1662+
; GFX11-NEXT: v_min_f16_e32 v0, INV2PI, v0
16631663
; GFX11-NEXT: v_mul_f16_e64 v0, -v0, v1
16641664
; GFX11-NEXT: s_setpc_b64 s[30:31]
16651665
; GFX11-SAFE-TRUE16-LABEL: v_fneg_inv2pi_minnum_foldable_use_f16:
16661666
; GFX11-SAFE-TRUE16: ; %bb.0:
16671667
; GFX11-SAFE-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
16681668
; GFX11-SAFE-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
16691669
; GFX11-SAFE-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
1670-
; GFX11-SAFE-TRUE16-NEXT: v_min_f16_e32 v0.l, 0.15915494, v0.l
1670+
; GFX11-SAFE-TRUE16-NEXT: v_min_f16_e32 v0.l, INV2PI, v0.l
16711671
; GFX11-SAFE-TRUE16-NEXT: v_mul_f16_e64 v0.l, -v0.l, v1.l
16721672
; GFX11-SAFE-TRUE16-NEXT: s_setpc_b64 s[30:31]
16731673
; GFX11-NSZ-TRUE16-LABEL: v_fneg_inv2pi_minnum_foldable_use_f16:
16741674
; GFX11-NSZ-TRUE16: ; %bb.0:
16751675
; GFX11-NSZ-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
16761676
; GFX11-NSZ-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
16771677
; GFX11-NSZ-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
1678-
; GFX11-NSZ-TRUE16-NEXT: v_min_f16_e32 v0.l, 0.15915494, v0.l
1678+
; GFX11-NSZ-TRUE16-NEXT: v_min_f16_e32 v0.l, INV2PI, v0.l
16791679
; GFX11-NSZ-TRUE16-NEXT: v_mul_f16_e64 v0.l, -v0.l, v1.l
16801680
; GFX11-NSZ-TRUE16-NEXT: s_setpc_b64 s[30:31]
16811681
%min = call half @llvm.minnum.f16(half 0xH3118, half %a)

‎llvm/test/CodeGen/AMDGPU/fneg-combines.ll‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1857,7 +1857,7 @@ define amdgpu_kernel void @v_fneg_inv2pi_minnum_f32(ptr addrspace(1) %out, ptr a
18571857
; VI-NEXT: v_mov_b32_e32 v1, s1
18581858
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
18591859
; VI-NEXT: v_mul_f32_e32 v2, 1.0, v3
1860-
; VI-NEXT: v_min_f32_e32 v2, 0.15915494, v2
1860+
; VI-NEXT: v_min_f32_e32 v2, INV2PI, v2
18611861
; VI-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
18621862
; VI-NEXT: flat_store_dword v[0:1], v2
18631863
; VI-NEXT: s_endpgm
@@ -1905,7 +1905,7 @@ define amdgpu_kernel void @v_fneg_neg_inv2pi_minnum_f32(ptr addrspace(1) %out, p
19051905
; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
19061906
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
19071907
; VI-NEXT: v_mul_f32_e32 v2, -1.0, v3
1908-
; VI-NEXT: v_max_f32_e32 v2, 0.15915494, v2
1908+
; VI-NEXT: v_max_f32_e32 v2, INV2PI, v2
19091909
; VI-NEXT: flat_store_dword v[0:1], v2
19101910
; VI-NEXT: s_endpgm
19111911
%tid = call i32 @llvm.amdgcn.workitem.id.x()
@@ -1953,7 +1953,7 @@ define amdgpu_kernel void @v_fneg_inv2pi_minnum_f16(ptr addrspace(1) %out, ptr a
19531953
; VI-NEXT: v_mov_b32_e32 v1, s1
19541954
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
19551955
; VI-NEXT: v_max_f16_e32 v2, v3, v3
1956-
; VI-NEXT: v_min_f16_e32 v2, 0.15915494, v2
1956+
; VI-NEXT: v_min_f16_e32 v2, INV2PI, v2
19571957
; VI-NEXT: v_xor_b32_e32 v2, 0x8000, v2
19581958
; VI-NEXT: flat_store_short v[0:1], v2
19591959
; VI-NEXT: s_endpgm
@@ -2002,7 +2002,7 @@ define amdgpu_kernel void @v_fneg_neg_inv2pi_minnum_f16(ptr addrspace(1) %out, p
20022002
; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
20032003
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
20042004
; VI-NEXT: v_max_f16_e64 v2, -v3, -v3
2005-
; VI-NEXT: v_max_f16_e32 v2, 0.15915494, v2
2005+
; VI-NEXT: v_max_f16_e32 v2, INV2PI, v2
20062006
; VI-NEXT: flat_store_short v[0:1], v2
20072007
; VI-NEXT: s_endpgm
20082008
%tid = call i32 @llvm.amdgcn.workitem.id.x()
@@ -2051,7 +2051,7 @@ define amdgpu_kernel void @v_fneg_inv2pi_minnum_f64(ptr addrspace(1) %out, ptr a
20512051
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
20522052
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
20532053
; VI-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1]
2054-
; VI-NEXT: v_min_f64 v[0:1], v[0:1], 0.15915494309189532
2054+
; VI-NEXT: v_min_f64 v[0:1], v[0:1], INV2PI
20552055
; VI-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
20562056
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
20572057
; VI-NEXT: s_endpgm
@@ -2101,7 +2101,7 @@ define amdgpu_kernel void @v_fneg_neg_inv2pi_minnum_f64(ptr addrspace(1) %out, p
21012101
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
21022102
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
21032103
; VI-NEXT: v_max_f64 v[0:1], -v[0:1], -v[0:1]
2104-
; VI-NEXT: v_max_f64 v[0:1], v[0:1], 0.15915494309189532
2104+
; VI-NEXT: v_max_f64 v[0:1], v[0:1], INV2PI
21052105
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
21062106
; VI-NEXT: s_endpgm
21072107
%tid = call i32 @llvm.amdgcn.workitem.id.x()
@@ -2235,7 +2235,7 @@ define amdgpu_kernel void @v_fneg_inv2pi_minnum_foldable_use_f32(ptr addrspace(1
22352235
; VI-NEXT: v_mov_b32_e32 v1, s1
22362236
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
22372237
; VI-NEXT: v_mul_f32_e32 v2, 1.0, v4
2238-
; VI-NEXT: v_min_f32_e32 v2, 0.15915494, v2
2238+
; VI-NEXT: v_min_f32_e32 v2, INV2PI, v2
22392239
; VI-NEXT: v_mul_f32_e64 v2, -v2, v3
22402240
; VI-NEXT: flat_store_dword v[0:1], v2
22412241
; VI-NEXT: s_endpgm

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