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[AArch64] Add v1i64 addsat/subsat (#142342)
Add basic handling for v1i64 saddsat, ssubsat, uaddsat and usubsat. We missed that these were not upgrading in #140454 due to a lack of test coverage, and for some reason the generic v1i64 nodes were not being treated as legal like they should. Fixes #142323
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9 files changed

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‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1336,7 +1336,7 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
13361336
setOperationAction(ISD::MUL, MVT::v1i64, Custom);
13371337

13381338
// Saturates
1339-
for (MVT VT : { MVT::v8i8, MVT::v4i16, MVT::v2i32,
1339+
for (MVT VT : { MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64,
13401340
MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
13411341
setOperationAction(ISD::SADDSAT, VT, Legal);
13421342
setOperationAction(ISD::UADDSAT, VT, Legal);

‎llvm/lib/Target/AArch64/AArch64InstrFormats.td‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7763,9 +7763,9 @@ multiclass SIMDThreeScalarD<bit U, bits<5> opc, string asm,
77637763
}
77647764

77657765
multiclass SIMDThreeScalarBHSD<bit U, bits<5> opc, string asm,
7766-
SDPatternOperator OpNode> {
7766+
SDPatternOperator OpNode, SDPatternOperator SatOp> {
77677767
def v1i64 : BaseSIMDThreeScalar<U, 0b111, opc, FPR64, asm,
7768-
[(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm)))]>;
7768+
[(set (v1i64 FPR64:$Rd), (SatOp (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm)))]>;
77697769
def v1i32 : BaseSIMDThreeScalar<U, 0b101, opc, FPR32, asm, []>;
77707770
def v1i16 : BaseSIMDThreeScalar<U, 0b011, opc, FPR16, asm, []>;
77717771
def v1i8 : BaseSIMDThreeScalar<U, 0b001, opc, FPR8 , asm, []>;

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -6339,19 +6339,19 @@ defm FCMGT : SIMDThreeScalarFPCmp<1, 1, 0b100, "fcmgt", AArch64fcmgt>;
63396339
defm FMULX : SIMDFPThreeScalar<0, 0, 0b011, "fmulx", int_aarch64_neon_fmulx, HasNEONandIsStreamingSafe>;
63406340
defm FRECPS : SIMDFPThreeScalar<0, 0, 0b111, "frecps", int_aarch64_neon_frecps, HasNEONandIsStreamingSafe>;
63416341
defm FRSQRTS : SIMDFPThreeScalar<0, 1, 0b111, "frsqrts", int_aarch64_neon_frsqrts, HasNEONandIsStreamingSafe>;
6342-
defm SQADD : SIMDThreeScalarBHSD<0, 0b00001, "sqadd", int_aarch64_neon_sqadd>;
6342+
defm SQADD : SIMDThreeScalarBHSD<0, 0b00001, "sqadd", int_aarch64_neon_sqadd, saddsat>;
63436343
defm SQDMULH : SIMDThreeScalarHS< 0, 0b10110, "sqdmulh", int_aarch64_neon_sqdmulh>;
63446344
defm SQRDMULH : SIMDThreeScalarHS< 1, 0b10110, "sqrdmulh", int_aarch64_neon_sqrdmulh>;
6345-
defm SQRSHL : SIMDThreeScalarBHSD<0, 0b01011, "sqrshl",int_aarch64_neon_sqrshl>;
6346-
defm SQSHL : SIMDThreeScalarBHSD<0, 0b01001, "sqshl", int_aarch64_neon_sqshl>;
6347-
defm SQSUB : SIMDThreeScalarBHSD<0, 0b00101, "sqsub", int_aarch64_neon_sqsub>;
6345+
defm SQRSHL : SIMDThreeScalarBHSD<0, 0b01011, "sqrshl", int_aarch64_neon_sqrshl, int_aarch64_neon_sqrshl>;
6346+
defm SQSHL : SIMDThreeScalarBHSD<0, 0b01001, "sqshl", int_aarch64_neon_sqshl, int_aarch64_neon_sqshl>;
6347+
defm SQSUB : SIMDThreeScalarBHSD<0, 0b00101, "sqsub", int_aarch64_neon_sqsub, ssubsat>;
63486348
defm SRSHL : SIMDThreeScalarD< 0, 0b01010, "srshl", int_aarch64_neon_srshl>;
63496349
defm SSHL : SIMDThreeScalarD< 0, 0b01000, "sshl", int_aarch64_neon_sshl>;
63506350
defm SUB : SIMDThreeScalarD< 1, 0b10000, "sub", sub>;
6351-
defm UQADD : SIMDThreeScalarBHSD<1, 0b00001, "uqadd", int_aarch64_neon_uqadd>;
6352-
defm UQRSHL : SIMDThreeScalarBHSD<1, 0b01011, "uqrshl",int_aarch64_neon_uqrshl>;
6353-
defm UQSHL : SIMDThreeScalarBHSD<1, 0b01001, "uqshl", int_aarch64_neon_uqshl>;
6354-
defm UQSUB : SIMDThreeScalarBHSD<1, 0b00101, "uqsub", int_aarch64_neon_uqsub>;
6351+
defm UQADD : SIMDThreeScalarBHSD<1, 0b00001, "uqadd", int_aarch64_neon_uqadd, uaddsat>;
6352+
defm UQRSHL : SIMDThreeScalarBHSD<1, 0b01011, "uqrshl", int_aarch64_neon_uqrshl, int_aarch64_neon_uqrshl>;
6353+
defm UQSHL : SIMDThreeScalarBHSD<1, 0b01001, "uqshl", int_aarch64_neon_uqshl, int_aarch64_neon_uqshl>;
6354+
defm UQSUB : SIMDThreeScalarBHSD<1, 0b00101, "uqsub", int_aarch64_neon_uqsub, usubsat>;
63556355
defm URSHL : SIMDThreeScalarD< 1, 0b01010, "urshl", int_aarch64_neon_urshl>;
63566356
defm USHL : SIMDThreeScalarD< 1, 0b01000, "ushl", int_aarch64_neon_ushl>;
63576357
let Predicates = [HasRDM] in {

‎llvm/test/CodeGen/AArch64/arm64-vqadd.ll‎

Lines changed: 2 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -45,13 +45,7 @@ define <1 x i64> @sqadd1d(ptr %A, ptr %B) nounwind {
4545
; CHECK: // %bb.0:
4646
; CHECK-NEXT: ldr d0, [x0]
4747
; CHECK-NEXT: ldr d1, [x1]
48-
; CHECK-NEXT: fmov x8, d1
49-
; CHECK-NEXT: fmov x9, d0
50-
; CHECK-NEXT: adds x8, x9, x8
51-
; CHECK-NEXT: asr x9, x8, #63
52-
; CHECK-NEXT: eor x9, x9, #0x8000000000000000
53-
; CHECK-NEXT: csel x8, x9, x8, vs
54-
; CHECK-NEXT: fmov d0, x8
48+
; CHECK-NEXT: sqadd d0, d0, d1
5549
; CHECK-NEXT: ret
5650
%tmp1 = load <1 x i64>, ptr %A
5751
%tmp2 = load <1 x i64>, ptr %B
@@ -104,11 +98,7 @@ define <1 x i64> @uqadd1d(ptr %A, ptr %B) nounwind {
10498
; CHECK: // %bb.0:
10599
; CHECK-NEXT: ldr d0, [x0]
106100
; CHECK-NEXT: ldr d1, [x1]
107-
; CHECK-NEXT: fmov x8, d1
108-
; CHECK-NEXT: fmov x9, d0
109-
; CHECK-NEXT: adds x8, x9, x8
110-
; CHECK-NEXT: csinv x8, x8, xzr, lo
111-
; CHECK-NEXT: fmov d0, x8
101+
; CHECK-NEXT: uqadd d0, d0, d1
112102
; CHECK-NEXT: ret
113103
%tmp1 = load <1 x i64>, ptr %A
114104
%tmp2 = load <1 x i64>, ptr %B

‎llvm/test/CodeGen/AArch64/arm64-vqsub.ll‎

Lines changed: 2 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -45,13 +45,7 @@ define <1 x i64> @sqsub1d(ptr %A, ptr %B) nounwind {
4545
; CHECK: // %bb.0:
4646
; CHECK-NEXT: ldr d0, [x0]
4747
; CHECK-NEXT: ldr d1, [x1]
48-
; CHECK-NEXT: fmov x8, d1
49-
; CHECK-NEXT: fmov x9, d0
50-
; CHECK-NEXT: subs x8, x9, x8
51-
; CHECK-NEXT: asr x9, x8, #63
52-
; CHECK-NEXT: eor x9, x9, #0x8000000000000000
53-
; CHECK-NEXT: csel x8, x9, x8, vs
54-
; CHECK-NEXT: fmov d0, x8
48+
; CHECK-NEXT: sqsub d0, d0, d1
5549
; CHECK-NEXT: ret
5650
%tmp1 = load <1 x i64>, ptr %A
5751
%tmp2 = load <1 x i64>, ptr %B
@@ -104,11 +98,7 @@ define <1 x i64> @uqsub1d(ptr %A, ptr %B) nounwind {
10498
; CHECK: // %bb.0:
10599
; CHECK-NEXT: ldr d0, [x0]
106100
; CHECK-NEXT: ldr d1, [x1]
107-
; CHECK-NEXT: fmov x8, d1
108-
; CHECK-NEXT: fmov x9, d0
109-
; CHECK-NEXT: subs x8, x9, x8
110-
; CHECK-NEXT: csel x8, xzr, x8, lo
111-
; CHECK-NEXT: fmov d0, x8
101+
; CHECK-NEXT: uqsub d0, d0, d1
112102
; CHECK-NEXT: ret
113103
%tmp1 = load <1 x i64>, ptr %A
114104
%tmp2 = load <1 x i64>, ptr %B

‎llvm/test/CodeGen/AArch64/sadd_sat_vec.ll‎

Lines changed: 3 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -447,13 +447,9 @@ define <16 x i32> @v16i32(<16 x i32> %x, <16 x i32> %y) nounwind {
447447
define void @v1i64(ptr %px, ptr %py, ptr %pz) nounwind {
448448
; CHECK-SD-LABEL: v1i64:
449449
; CHECK-SD: // %bb.0:
450-
; CHECK-SD-NEXT: ldr x8, [x1]
451-
; CHECK-SD-NEXT: ldr x9, [x0]
452-
; CHECK-SD-NEXT: adds x8, x9, x8
453-
; CHECK-SD-NEXT: asr x9, x8, #63
454-
; CHECK-SD-NEXT: eor x9, x9, #0x8000000000000000
455-
; CHECK-SD-NEXT: csel x8, x9, x8, vs
456-
; CHECK-SD-NEXT: fmov d0, x8
450+
; CHECK-SD-NEXT: ldr d0, [x0]
451+
; CHECK-SD-NEXT: ldr d1, [x1]
452+
; CHECK-SD-NEXT: sqadd d0, d0, d1
457453
; CHECK-SD-NEXT: str d0, [x2]
458454
; CHECK-SD-NEXT: ret
459455
;

‎llvm/test/CodeGen/AArch64/ssub_sat_vec.ll‎

Lines changed: 3 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -449,13 +449,9 @@ define <16 x i32> @v16i32(<16 x i32> %x, <16 x i32> %y) nounwind {
449449
define void @v1i64(ptr %px, ptr %py, ptr %pz) nounwind {
450450
; CHECK-SD-LABEL: v1i64:
451451
; CHECK-SD: // %bb.0:
452-
; CHECK-SD-NEXT: ldr x8, [x1]
453-
; CHECK-SD-NEXT: ldr x9, [x0]
454-
; CHECK-SD-NEXT: subs x8, x9, x8
455-
; CHECK-SD-NEXT: asr x9, x8, #63
456-
; CHECK-SD-NEXT: eor x9, x9, #0x8000000000000000
457-
; CHECK-SD-NEXT: csel x8, x9, x8, vs
458-
; CHECK-SD-NEXT: fmov d0, x8
452+
; CHECK-SD-NEXT: ldr d0, [x0]
453+
; CHECK-SD-NEXT: ldr d1, [x1]
454+
; CHECK-SD-NEXT: sqsub d0, d0, d1
459455
; CHECK-SD-NEXT: str d0, [x2]
460456
; CHECK-SD-NEXT: ret
461457
;

‎llvm/test/CodeGen/AArch64/uadd_sat_vec.ll‎

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -439,11 +439,9 @@ define <16 x i32> @v16i32(<16 x i32> %x, <16 x i32> %y) nounwind {
439439
define void @v1i64(ptr %px, ptr %py, ptr %pz) nounwind {
440440
; CHECK-SD-LABEL: v1i64:
441441
; CHECK-SD: // %bb.0:
442-
; CHECK-SD-NEXT: ldr x8, [x1]
443-
; CHECK-SD-NEXT: ldr x9, [x0]
444-
; CHECK-SD-NEXT: adds x8, x9, x8
445-
; CHECK-SD-NEXT: csinv x8, x8, xzr, lo
446-
; CHECK-SD-NEXT: fmov d0, x8
442+
; CHECK-SD-NEXT: ldr d0, [x0]
443+
; CHECK-SD-NEXT: ldr d1, [x1]
444+
; CHECK-SD-NEXT: uqadd d0, d0, d1
447445
; CHECK-SD-NEXT: str d0, [x2]
448446
; CHECK-SD-NEXT: ret
449447
;

‎llvm/test/CodeGen/AArch64/usub_sat_vec.ll‎

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -436,11 +436,9 @@ define <16 x i32> @v16i32(<16 x i32> %x, <16 x i32> %y) nounwind {
436436
define void @v1i64(ptr %px, ptr %py, ptr %pz) nounwind {
437437
; CHECK-SD-LABEL: v1i64:
438438
; CHECK-SD: // %bb.0:
439-
; CHECK-SD-NEXT: ldr x8, [x1]
440-
; CHECK-SD-NEXT: ldr x9, [x0]
441-
; CHECK-SD-NEXT: subs x8, x9, x8
442-
; CHECK-SD-NEXT: csel x8, xzr, x8, lo
443-
; CHECK-SD-NEXT: fmov d0, x8
439+
; CHECK-SD-NEXT: ldr d0, [x0]
440+
; CHECK-SD-NEXT: ldr d1, [x1]
441+
; CHECK-SD-NEXT: uqsub d0, d0, d1
444442
; CHECK-SD-NEXT: str d0, [x2]
445443
; CHECK-SD-NEXT: ret
446444
;

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