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[RISCV] Support Zfa in SiFive P600's scheduling model
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‎llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td‎

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -283,6 +283,9 @@ def : WriteRes<WriteFCvtF64ToI32, [SiFiveP600F2I]>;
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def : WriteRes<WriteFCvtF64ToI64, [SiFiveP600F2I]>;
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def : WriteRes<WriteFCvtF64ToF16, [SiFiveP600FloatArith]>;
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def : WriteRes<WriteFCvtF64ToF32, [SiFiveP600FloatArith]>;
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def : WriteRes<WriteFRoundF16, [SiFiveP600FloatArith]>;
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def : WriteRes<WriteFRoundF32, [SiFiveP600FloatArith]>;
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def : WriteRes<WriteFRoundF64, [SiFiveP600FloatArith]>;
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def : WriteRes<WriteFClass16, [SiFiveP600F2I]>;
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def : WriteRes<WriteFClass32, [SiFiveP600F2I]>;
@@ -296,6 +299,9 @@ def : WriteRes<WriteFMovI32ToF32, [SiFiveP600MulI2F]>;
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def : WriteRes<WriteFMovF32ToI32, [SiFiveP600F2I]>;
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def : WriteRes<WriteFMovI64ToF64, [SiFiveP600MulI2F]>;
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def : WriteRes<WriteFMovF64ToI64, [SiFiveP600F2I]>;
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def : WriteRes<WriteFLI16, [SiFiveP600MulI2F]>;
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def : WriteRes<WriteFLI32, [SiFiveP600MulI2F]>;
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def : WriteRes<WriteFLI64, [SiFiveP600MulI2F]>;
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}
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// 6. Configuration-Setting Instructions
@@ -893,6 +899,9 @@ def : ReadAdvance<ReadFCvtF16ToF32, 0>;
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def : ReadAdvance<ReadFCvtF32ToF16, 0>;
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def : ReadAdvance<ReadFCvtF16ToF64, 0>;
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def : ReadAdvance<ReadFCvtF64ToF16, 0>;
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def : ReadAdvance<ReadFRoundF16, 0>;
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def : ReadAdvance<ReadFRoundF32, 0>;
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def : ReadAdvance<ReadFRoundF64, 0>;
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def : ReadAdvance<ReadFMovF16ToI16, 0>;
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def : ReadAdvance<ReadFMovI16ToF16, 0>;
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def : ReadAdvance<ReadFMovF32ToI32, 0>;
@@ -1140,6 +1149,5 @@ defm : UnsupportedSchedZbc;
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defm : UnsupportedSchedZbkb;
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defm : UnsupportedSchedZbkx;
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defm : UnsupportedSchedSFB;
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defm : UnsupportedSchedZfa;
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defm : UnsupportedSchedXsfvcp;
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}

‎llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zfa.s‎

Lines changed: 76 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,76 @@
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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -mattr=+zfa,+zfh -iterations=1 < %s | FileCheck %s
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fli.h fa5, nan
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fli.s fa5, nan
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fli.d fa5, nan
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fround.h fa0, fa0, rdn
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froundnx.h fa0, fa0, rdn
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fround.s fa0, fa0, rdn
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froundnx.s fa0, fa0, rdn
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fround.d fa0, fa0, rdn
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froundnx.d fa0, fa0, rdn
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# CHECK: Iterations: 1
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# CHECK-NEXT: Instructions: 9
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# CHECK-NEXT: Total Cycles: 15
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# CHECK-NEXT: Total uOps: 9
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# CHECK: Dispatch Width: 4
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# CHECK-NEXT: uOps Per Cycle: 0.60
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# CHECK-NEXT: IPC: 0.60
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# CHECK-NEXT: Block RThroughput: 3.0
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# CHECK: Instruction Info:
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# CHECK-NEXT: [1]: #uOps
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# CHECK-NEXT: [2]: Latency
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# CHECK-NEXT: [3]: RThroughput
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# CHECK-NEXT: [4]: MayLoad
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# CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: [6]: HasSideEffects (U)
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# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
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# CHECK-NEXT: 1 2 1.00 fli.h fa5, nan
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# CHECK-NEXT: 1 2 1.00 fli.s fa5, nan
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# CHECK-NEXT: 1 2 1.00 fli.d fa5, nan
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# CHECK-NEXT: 1 2 0.50 fround.h fa0, fa0, rdn
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# CHECK-NEXT: 1 2 0.50 froundnx.h fa0, fa0, rdn
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# CHECK-NEXT: 1 2 0.50 fround.s fa0, fa0, rdn
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# CHECK-NEXT: 1 2 0.50 froundnx.s fa0, fa0, rdn
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# CHECK-NEXT: 1 2 0.50 fround.d fa0, fa0, rdn
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# CHECK-NEXT: 1 2 0.50 froundnx.d fa0, fa0, rdn
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# CHECK: Resources:
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# CHECK-NEXT: [0] - SiFiveP600Div
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# CHECK-NEXT: [1] - SiFiveP600FEXQ0
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# CHECK-NEXT: [2] - SiFiveP600FEXQ1
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# CHECK-NEXT: [3] - SiFiveP600FloatDiv
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# CHECK-NEXT: [4] - SiFiveP600IEXQ0
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# CHECK-NEXT: [5] - SiFiveP600IEXQ1
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# CHECK-NEXT: [6] - SiFiveP600IEXQ2
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# CHECK-NEXT: [7] - SiFiveP600IEXQ3
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# CHECK-NEXT: [8.0] - SiFiveP600LDST
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# CHECK-NEXT: [8.1] - SiFiveP600LDST
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# CHECK-NEXT: [9] - SiFiveP600VDiv
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# CHECK-NEXT: [10] - SiFiveP600VEXQ0
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# CHECK-NEXT: [11] - SiFiveP600VEXQ1
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# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
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# CHECK-NEXT: [13] - SiFiveP600VLD
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# CHECK-NEXT: [14] - SiFiveP600VST
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# CHECK: Resource pressure per iteration:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
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# CHECK-NEXT: - 3.00 3.00 - - 3.00 - - - - - - - - - -
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
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# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - fli.h fa5, nan
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# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - fli.s fa5, nan
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# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - fli.d fa5, nan
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - fround.h fa0, fa0, rdn
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# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - froundnx.h fa0, fa0, rdn
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - fround.s fa0, fa0, rdn
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# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - froundnx.s fa0, fa0, rdn
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# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - fround.d fa0, fa0, rdn
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# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - froundnx.d fa0, fa0, rdn

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