Move isArtificialRegUnit to MCRegisterInfo

Author: sdesmalen-arm

llvm/include/llvm/CodeGen/MachineRegisterInfo.h

@@ -980,12 +980,6 @@ class MachineRegisterInfo {
   /// expected.
   bool isReservedRegUnit(unsigned Unit) const;
 
-  /// Returns true when the given register unit is considered artificial.
-  ///
-  /// Register units are considered artificial when at least one of the
-  /// root registers is artificial.
-  bool isArtificialRegUnit(unsigned Unit) const;
-
   /// isAllocatable - Returns true when PhysReg belongs to an allocatable
   /// register class and it hasn't been reserved.
   ///

llvm/include/llvm/MC/MCRegisterInfo.h

@@ -404,6 +404,11 @@ class MCRegisterInfo {
   /// be modelled, such as the top 16-bits of a 32-bit GPR.
   bool isArtificial(MCRegister RegNo) const { return get(RegNo).IsArtificial; }
 
+  /// Returns true when the given register unit is considered artificial.
+  /// Register units are considered artificial when at least one of the
+  /// root registers is artificial.
+  bool isArtificialRegUnit(MCRegUnit Unit) const;
+
   /// Return the number of registers this target has (useful for
   /// sizing arrays holding per register information)
   unsigned getNumRegs() const {

llvm/lib/CodeGen/LiveIntervals.cpp

@@ -734,7 +734,7 @@ void LiveIntervals::addKillFlags(const VirtRegMap *VRM) {
     for (MCRegUnitMaskIterator UI(PhysReg, TRI); UI.isValid(); ++UI) {
       auto [Unit, Bitmask] = *UI;
       // Record lane mask for all artificial RegUnits for this physreg.
-      if (MRI->isArtificialRegUnit(Unit))
+      if (TRI->isArtificialRegUnit(Unit))
         ArtificialLanes |= Bitmask;
       const LiveRange &RURange = getRegUnit(Unit);
       if (RURange.empty())

llvm/lib/CodeGen/MachineRegisterInfo.cpp

@@ -659,11 +659,3 @@ bool MachineRegisterInfo::isReservedRegUnit(unsigned Unit) const {
   }
   return false;
 }
-
-bool MachineRegisterInfo::isArtificialRegUnit(unsigned Unit) const {
-  const TargetRegisterInfo *TRI = getTargetRegisterInfo();
-  for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root)
-    if (TRI->isArtificial(*Root))
-      return true;
-  return false;
-}

llvm/lib/MC/MCRegisterInfo.cpp

@@ -220,3 +220,10 @@ bool MCRegisterInfo::regsOverlap(MCRegister RegA, MCRegister RegB) const {
   } while (*IA < *IB ? ++IA != EA : ++IB != EB);
   return false;
 }
+
+bool MCRegisterInfo::isArtificialRegUnit(unsigned Unit) const {
+  for (MCRegUnitRootIterator Root(Unit, this); Root.isValid(); ++Root)
+    if (isArtificial(*Root))
+      return true;
+  return false;
+}