[SLP]Do not match nodes if schedulability of parent nodes is different

If one user node is non-schedulable and another one is schedulable, such
nodes should be considered matched. The selection of the actual insert
point in this case differs and the insert points may match, which may
cause a compiler crash because of the broken def-use chain.

Fixes #137797

Author: alexey-bataev

llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp

@@ -15245,6 +15245,11 @@ BoUpSLP::isGatherShuffledSingleRegisterEntry(
           continue;
       }
 
+      if (!TEUseEI.UserTE->isGather() && !UserPHI &&
+          doesNotNeedToSchedule(TEUseEI.UserTE->Scalars) !=
+              doesNotNeedToSchedule(UseEI.UserTE->Scalars) &&
+          is_contained(UseEI.UserTE->Scalars, TEInsertPt))
+        continue;
       // Check if the user node of the TE comes after user node of TEPtr,
       // otherwise TEPtr depends on TE.
       if ((TEInsertBlock != InsertPt->getParent() ||

llvm/test/Transforms/SLPVectorizer/X86/matched-bv-schedulable.ll

@@ -0,0 +1,39 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu < %s -slp-threshold=-99999 | FileCheck %s
+
+define void @test() {
+; CHECK-LABEL: define void @test() {
+; CHECK-NEXT:  [[BB:.*]]:
+; CHECK-NEXT:    br i1 false, label %[[BB1:.*]], label %[[BB5:.*]]
+; CHECK:       [[BB1]]:
+; CHECK-NEXT:    [[TMP0:%.*]] = phi <2 x i32> [ [[TMP3:%.*]], %[[BB1]] ], [ zeroinitializer, %[[BB]] ]
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <2 x i32> [[TMP0]], <2 x i32> <i32 poison, i32 0>, <2 x i32> <i32 0, i32 3>
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x i32> <i32 poison, i32 1>, i32 0, i32 0
+; CHECK-NEXT:    [[TMP3]] = or <2 x i32> [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    [[TMP4:%.*]] = insertelement <2 x i32> <i32 poison, i32 0>, i32 0, i32 0
+; CHECK-NEXT:    [[TMP5:%.*]] = or <2 x i32> [[TMP0]], [[TMP4]]
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <2 x i32> [[TMP5]], i32 1
+; CHECK-NEXT:    [[OR3:%.*]] = or i32 [[TMP6]], 0
+; CHECK-NEXT:    br i1 false, label %[[BB1]], label %[[BB5]]
+; CHECK:       [[BB5]]:
+; CHECK-NEXT:    [[TMP7:%.*]] = phi <2 x i32> [ zeroinitializer, %[[BB]] ], [ [[TMP5]], %[[BB1]] ]
+; CHECK-NEXT:    ret void
+;
+bb:
+  br i1 false, label %bb1, label %bb5
+
+bb1:
+  %phi = phi i32 [ %or4, %bb1 ], [ 0, %bb ]
+  %phi2 = phi i32 [ %add, %bb1 ], [ 0, %bb ]
+  %add = add i32 1, 0
+  %or = or i32 0, %phi2
+  %or3 = or i32 %or, 0
+  %mul = mul i32 0, 0
+  %or4 = or i32 %phi, %mul
+  br i1 false, label %bb1, label %bb5
+
+bb5:
+  %phi6 = phi i32 [ 0, %bb ], [ %or4, %bb1 ]
+  %phi7 = phi i32 [ 0, %bb ], [ %or, %bb1 ]
+  ret void
+}