change uimm5_zibi to imm5_zibi

Author: BoyaoWang430

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

@@ -745,11 +745,6 @@ struct RISCVOperand final : public MCParsedAsmOperand {
     return isUImmPred([](int64_t Imm) { return Imm != 0 && isUInt<5>(Imm); });
   }
 
-  bool isUImm5Zibi() const {
-    return isUImmPred(
-        [](int64_t Imm) { return (Imm != 0 && isUInt<5>(Imm)) || Imm == -1; });
-  }
-
   bool isUImm5GT3() const {
     return isUImmPred([](int64_t Imm) { return isUInt<5>(Imm) && Imm > 3; });
   }
@@ -951,6 +946,11 @@ struct RISCVOperand final : public MCParsedAsmOperand {
     return isUImmPred([](int64_t Imm) { return 4 == Imm; });
   }
 
+  bool isImm5Zibi() const {
+    return isUImmPred(
+        [](int64_t Imm) { return (Imm != 0 && isUInt<5>(Imm)) || Imm == -1; });
+  }
+
   bool isSImm5Plus1() const {
     return isSImmPred(
         [](int64_t Imm) { return Imm != INT64_MIN && isInt<5>(Imm - 1); });
@@ -1493,10 +1493,6 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
     return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 5) - 1);
   case Match_InvalidUImm5NonZero:
     return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 5) - 1);
-  case Match_InvalidUImm5Zibi:
-    return generateImmOutOfRangeError(
-        Operands, ErrorInfo, -1, (1 << 5) - 1,
-        "immediate must be non-zero in the range");
   case Match_InvalidUImm5GT3:
     return generateImmOutOfRangeError(Operands, ErrorInfo, 4, (1 << 5) - 1);
   case Match_InvalidUImm5Plus1:
@@ -1652,6 +1648,10 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
                                       "operand must be a valid system register "
                                       "name or an integer in the range");
   }
+  case Match_InvalidImm5Zibi:
+    return generateImmOutOfRangeError(
+        Operands, ErrorInfo, -1, (1 << 5) - 1,
+        "immediate must be non-zero in the range");
   case Match_InvalidVTypeI: {
     SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
     return generateVTypeError(ErrorLoc);

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

@@ -461,14 +461,6 @@ static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint32_t Imm,
   return decodeUImmOperand<N>(Inst, Imm, Address, Decoder);
 }
 
-static DecodeStatus decodeUImmZibiOperand(MCInst &Inst, uint32_t Imm,
-                                          int64_t Address,
-                                          const MCDisassembler *Decoder) {
-  assert(isUInt<5>(Imm) && "Invalid immediate");
-  Inst.addOperand(MCOperand::createImm(Imm ? Imm : -1LL));
-  return MCDisassembler::Success;
-}
-
 static DecodeStatus
 decodeUImmLog2XLenNonZeroOperand(MCInst &Inst, uint32_t Imm, int64_t Address,
                                  const MCDisassembler *Decoder) {
@@ -486,6 +478,14 @@ static DecodeStatus decodeUImmPlus1Operand(MCInst &Inst, uint32_t Imm,
   return MCDisassembler::Success;
 }
 
+static DecodeStatus decodeImmZibiOperand(MCInst &Inst, uint32_t Imm,
+                                         int64_t Address,
+                                         const MCDisassembler *Decoder) {
+  assert(isUInt<5>(Imm) && "Invalid immediate");
+  Inst.addOperand(MCOperand::createImm(Imm ? Imm : -1LL));
+  return MCDisassembler::Success;
+}
+
 template <unsigned N>
 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint32_t Imm,
                                       int64_t Address,

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

@@ -310,7 +310,6 @@ enum OperandType : unsigned {
   OPERAND_UIMM4,
   OPERAND_UIMM5,
   OPERAND_UIMM5_NONZERO,
-  OPERAND_UIMM5_ZIBI,
   OPERAND_UIMM5_GT3,
   OPERAND_UIMM5_PLUS1,
   OPERAND_UIMM5_GE6_PLUS1,
@@ -342,6 +341,7 @@ enum OperandType : unsigned {
   OPERAND_UIMM64,
   OPERAND_THREE,
   OPERAND_FOUR,
+  OPERAND_IMM5_ZIBI,
   OPERAND_SIMM5,
   OPERAND_SIMM5_NONZERO,
   OPERAND_SIMM5_PLUS1,

llvm/lib/Target/RISCV/RISCVInstrInfoZibi.td

@@ -11,24 +11,24 @@
 //===----------------------------------------------------------------------===//
 
 // A 5-bit unsigned immediate representing 1-31 and -1. 00000 represents -1.
-def uimm5_zibi : RISCVOp<XLenVT>, ImmLeaf<XLenVT, [{
+def imm5_zibi : RISCVOp<XLenVT>, ImmLeaf<XLenVT, [{
     return (Imm != 0 && isUInt<5>(Imm)) || Imm == -1;
 }]> {
-  let ParserMatchClass = UImmAsmOperand<5, "Zibi">;
+  let ParserMatchClass = ImmAsmOperand<"", 5, "Zibi">;
   let EncoderMethod = "getImmOpValueZibi";
-  let DecoderMethod = "decodeUImmZibiOperand";
+  let DecoderMethod = "decodeImmZibiOperand";
   let MCOperandPredicate = [{
     int64_t Imm;
     if (!MCOp.evaluateAsConstantImm(Imm))
       return false;
     return (Imm >= 1 && Imm <= 31) || Imm == -1;
   }];
-  let OperandType = "OPERAND_UIMM5_ZIBI";
+  let OperandType = "OPERAND_IMM5_ZIBI";
 }
 
 class Branch_imm<bits<3> funct3, string opcodestr>
     : RVInstBIMM<funct3, OPC_BRANCH, (outs),
-                 (ins GPR:$rs1, uimm5_zibi:$cimm, bare_simm13_lsb0:$imm12),
+                 (ins GPR:$rs1, imm5_zibi:$cimm, bare_simm13_lsb0:$imm12),
                  opcodestr, "$rs1, $cimm, $imm12">,
       Sched<[WriteJmp, ReadJmp]> {
   let isBranch = 1;