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[RISCV] Fix illegal build_vector when lowering double id buildvec on RV32 (#67017)
When lowering a constant build_vector sequence of doubles on RV32, if the addend wasn't zero, or the step/denominator wasn't one, it would crash trying to emit an illegal build_vector of <n x i64> with i32 operands, e.g: t15: v2i64 = BUILD_VECTOR Constant:i32<1>, Constant:i32<1> This patch fixes this by lowering the splats with SelectionDAG::getConstant with the vector type, which handles making it legal via splat_vector_parts.
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lines changed

3 files changed

+134
-7
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp‎

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -3392,18 +3392,16 @@ static SDValue lowerBuildVectorOfConstants(SDValue Op, SelectionDAG &DAG,
33923392
VID = convertFromScalableVector(VIDVT, VID, DAG, Subtarget);
33933393
if ((StepOpcode == ISD::MUL && SplatStepVal != 1) ||
33943394
(StepOpcode == ISD::SHL && SplatStepVal != 0)) {
3395-
SDValue SplatStep = DAG.getSplatBuildVector(
3396-
VIDVT, DL, DAG.getConstant(SplatStepVal, DL, XLenVT));
3395+
SDValue SplatStep = DAG.getConstant(SplatStepVal, DL, VIDVT);
33973396
VID = DAG.getNode(StepOpcode, DL, VIDVT, VID, SplatStep);
33983397
}
33993398
if (StepDenominator != 1) {
3400-
SDValue SplatStep = DAG.getSplatBuildVector(
3401-
VIDVT, DL, DAG.getConstant(Log2_64(StepDenominator), DL, XLenVT));
3399+
SDValue SplatStep =
3400+
DAG.getConstant(Log2_64(StepDenominator), DL, VIDVT);
34023401
VID = DAG.getNode(ISD::SRL, DL, VIDVT, VID, SplatStep);
34033402
}
34043403
if (Addend != 0 || Negate) {
3405-
SDValue SplatAddend = DAG.getSplatBuildVector(
3406-
VIDVT, DL, DAG.getConstant(Addend, DL, XLenVT));
3404+
SDValue SplatAddend = DAG.getConstant(Addend, DL, VIDVT);
34073405
VID = DAG.getNode(Negate ? ISD::SUB : ISD::ADD, DL, VIDVT, SplatAddend,
34083406
VID);
34093407
}

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll‎

Lines changed: 129 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1083,3 +1083,132 @@ define <2 x float> @signbits() {
10831083
entry:
10841084
ret <2 x float> <float 0x36A0000000000000, float 0.000000e+00>
10851085
}
1086+
1087+
define <2 x half> @vid_v2f16() {
1088+
; CHECK-LABEL: vid_v2f16:
1089+
; CHECK: # %bb.0:
1090+
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
1091+
; CHECK-NEXT: vid.v v8
1092+
; CHECK-NEXT: vfcvt.f.x.v v8, v8
1093+
; CHECK-NEXT: ret
1094+
ret <2 x half> <half 0.0, half 1.0>
1095+
}
1096+
1097+
define <2 x half> @vid_addend1_v2f16() {
1098+
; CHECK-LABEL: vid_addend1_v2f16:
1099+
; CHECK: # %bb.0:
1100+
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
1101+
; CHECK-NEXT: vid.v v8
1102+
; CHECK-NEXT: vadd.vi v8, v8, 1
1103+
; CHECK-NEXT: vfcvt.f.x.v v8, v8
1104+
; CHECK-NEXT: ret
1105+
ret <2 x half> <half 1.0, half 2.0>
1106+
}
1107+
1108+
define <2 x half> @vid_denominator2_v2f16() {
1109+
; CHECK-LABEL: vid_denominator2_v2f16:
1110+
; CHECK: # %bb.0:
1111+
; CHECK-NEXT: lui a0, %hi(.LCPI27_0)
1112+
; CHECK-NEXT: addi a0, a0, %lo(.LCPI27_0)
1113+
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
1114+
; CHECK-NEXT: vle16.v v8, (a0)
1115+
; CHECK-NEXT: ret
1116+
ret <2 x half> <half 0.5, half 1.0>
1117+
}
1118+
1119+
define <2 x half> @vid_step2_v2f16() {
1120+
; CHECK-LABEL: vid_step2_v2f16:
1121+
; CHECK: # %bb.0:
1122+
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
1123+
; CHECK-NEXT: vid.v v8
1124+
; CHECK-NEXT: vadd.vv v8, v8, v8
1125+
; CHECK-NEXT: vfcvt.f.x.v v8, v8
1126+
; CHECK-NEXT: ret
1127+
ret <2 x half> <half 0.0, half 2.0>
1128+
}
1129+
1130+
define <2 x float> @vid_v2f32() {
1131+
; CHECK-LABEL: vid_v2f32:
1132+
; CHECK: # %bb.0:
1133+
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
1134+
; CHECK-NEXT: vid.v v8
1135+
; CHECK-NEXT: vfcvt.f.x.v v8, v8
1136+
; CHECK-NEXT: ret
1137+
ret <2 x float> <float 0.0, float 1.0>
1138+
}
1139+
1140+
define <2 x float> @vid_addend1_v2f32() {
1141+
; CHECK-LABEL: vid_addend1_v2f32:
1142+
; CHECK: # %bb.0:
1143+
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
1144+
; CHECK-NEXT: vid.v v8
1145+
; CHECK-NEXT: vadd.vi v8, v8, 1
1146+
; CHECK-NEXT: vfcvt.f.x.v v8, v8
1147+
; CHECK-NEXT: ret
1148+
ret <2 x float> <float 1.0, float 2.0>
1149+
}
1150+
1151+
define <2 x float> @vid_denominator2_v2f32() {
1152+
; CHECK-LABEL: vid_denominator2_v2f32:
1153+
; CHECK: # %bb.0:
1154+
; CHECK-NEXT: lui a0, %hi(.LCPI31_0)
1155+
; CHECK-NEXT: addi a0, a0, %lo(.LCPI31_0)
1156+
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
1157+
; CHECK-NEXT: vle32.v v8, (a0)
1158+
; CHECK-NEXT: ret
1159+
ret <2 x float> <float 0.5, float 1.0>
1160+
}
1161+
1162+
define <2 x float> @vid_step2_v2f32() {
1163+
; CHECK-LABEL: vid_step2_v2f32:
1164+
; CHECK: # %bb.0:
1165+
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
1166+
; CHECK-NEXT: vid.v v8
1167+
; CHECK-NEXT: vadd.vv v8, v8, v8
1168+
; CHECK-NEXT: vfcvt.f.x.v v8, v8
1169+
; CHECK-NEXT: ret
1170+
ret <2 x float> <float 0.0, float 2.0>
1171+
}
1172+
1173+
define <2 x double> @vid_v2f64() {
1174+
; CHECK-LABEL: vid_v2f64:
1175+
; CHECK: # %bb.0:
1176+
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
1177+
; CHECK-NEXT: vid.v v8
1178+
; CHECK-NEXT: vfcvt.f.x.v v8, v8
1179+
; CHECK-NEXT: ret
1180+
ret <2 x double> <double 0.0, double 1.0>
1181+
}
1182+
1183+
define <2 x double> @vid_addend1_v2f64() {
1184+
; CHECK-LABEL: vid_addend1_v2f64:
1185+
; CHECK: # %bb.0:
1186+
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
1187+
; CHECK-NEXT: vid.v v8
1188+
; CHECK-NEXT: vadd.vi v8, v8, 1
1189+
; CHECK-NEXT: vfcvt.f.x.v v8, v8
1190+
; CHECK-NEXT: ret
1191+
ret <2 x double> <double 1.0, double 2.0>
1192+
}
1193+
1194+
define <2 x double> @vid_denominator2_v2f64() {
1195+
; CHECK-LABEL: vid_denominator2_v2f64:
1196+
; CHECK: # %bb.0:
1197+
; CHECK-NEXT: lui a0, %hi(.LCPI35_0)
1198+
; CHECK-NEXT: addi a0, a0, %lo(.LCPI35_0)
1199+
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
1200+
; CHECK-NEXT: vle64.v v8, (a0)
1201+
; CHECK-NEXT: ret
1202+
ret <2 x double> <double 0.5, double 1.0>
1203+
}
1204+
1205+
define <2 x double> @vid_step2_v2f64() {
1206+
; CHECK-LABEL: vid_step2_v2f64:
1207+
; CHECK: # %bb.0:
1208+
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
1209+
; CHECK-NEXT: vid.v v8
1210+
; CHECK-NEXT: vadd.vv v8, v8, v8
1211+
; CHECK-NEXT: vfcvt.f.x.v v8, v8
1212+
; CHECK-NEXT: ret
1213+
ret <2 x double> <double 0.0, double 2.0>
1214+
}

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -259,7 +259,7 @@ define <4 x i8> @buildvec_vid_stepn3_add3_v4i8() {
259259
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
260260
; CHECK-NEXT: vmv.v.i v9, 3
261261
; CHECK-NEXT: vid.v v8
262-
; CHECK-NEXT: li a0, -3
262+
; CHECK-NEXT: li a0, 253
263263
; CHECK-NEXT: vmadd.vx v8, a0, v9
264264
; CHECK-NEXT: ret
265265
ret <4 x i8> <i8 3, i8 0, i8 -3, i8 -6>

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