Changing two symbolic names to one

Author: jwanggit86

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

@@ -2409,8 +2409,10 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
     case AMDGPU::OPERAND_REG_INLINE_C_BF16:
     case AMDGPU::OPERAND_REG_INLINE_C_V2BF16:
     case AMDGPU::OPERAND_REG_IMM_V2BF16:
+      // If the symbol INV2PI is used as the operand, the value is set to
+      // 0x3fc45f306dc9c882 in parseImm().
       if (Lit == LitModifier::None && AsmParser->hasInv2PiInlineImm() &&
-          Literal == 0x3fc45f306725feed) {
+          (Literal == 0x3fc45f306725feed || Literal == 0x3fc45f306dc9c882)) {
         // This is the 1/(2*pi) which is going to be truncated to bf16 with the
         // loss of precision. The constant represents ideomatic fp32 value of
         // 1/(2*pi) = 0.15915494 since bf16 is in fact fp32 with cleared low 16
@@ -3229,10 +3231,7 @@ AMDGPUAsmParser::parseRegister(bool RestoreOnFailure) {
 }
 
 static bool isInv2PiToken(const AsmToken &Tok) {
-  if (!Tok.is(AsmToken::Identifier))
-    return false;
-  StringRef Str = Tok.getIdentifier();
-  return (Str.str() == "INV2PI" || Str.str() == "INV2PI64");
+  return Tok.is(AsmToken::Identifier) && Tok.getIdentifier() == "INV2PI";
 }
 
 ParseStatus AMDGPUAsmParser::parseImm(OperandVector &Operands,
@@ -3281,9 +3280,9 @@ ParseStatus AMDGPUAsmParser::parseImm(OperandVector &Operands,
     // optional sign.
 
     StringRef Num = getTokenStr();
-    if (Num.str() == "INV2PI")
-      Num = "0.15915494";
-    else if (Num.str() == "INV2PI64")
+    if (Num == "INV2PI")
+      // Setting the imm to this for INV2PI works for all types except bf16.
+      // In addLiteralImmOperand() we specifically check for this.
       Num = "0.15915494309189532";
     lex();
 

llvm/test/MC/AMDGPU/bf16_imm-fake16.s

@@ -83,10 +83,6 @@ v_dot2_f32_bf16 v2, v1, 0.15915494, v2
 v_dot2_f32_bf16 v2, v1, INV2PI, v2
 // CHECK: v_dot2_f32_bf16 v2, v1, 0.15915494, v2  ; encoding: [0x02,0x40,0x1a,0xcc,0x01,0xf1,0x09,0x1c]
 
-// INV2PI64 is not interpreted as INV2PI
-v_dot2_f32_bf16 v2, v1, INV2PI64, v2
-// CHECK: v_dot2_f32_bf16 v2, v1, 0x3e23, v2      ; encoding: [0x02,0x40,0x1a,0xcc,0x01,0xff,0x09,0x1c,0x23,0x3e,0x00,0x00]
-
 v_dot2_f32_bf16 v2, v1, 0x3e22, v2
 // CHECK: v_dot2_f32_bf16 v2, v1, 0.15915494, v2  ; encoding: [0x02,0x40,0x1a,0xcc,0x01,0xf1,0x09,0x1c]
 

llvm/test/MC/AMDGPU/gfx1250_asm_valu_lit64.s

@@ -235,12 +235,8 @@ v_ceil_f64 v[254:255], 0x3fc45f306dc9c882
 v_ceil_f64 v[254:255], 0.15915494309189532
 // GFX1250: v_ceil_f64_e32 v[254:255], 0.15915494309189532 ; encoding: [0xf8,0x30,0xfc,0x7f]
 
-v_ceil_f64 v[254:255], INV2PI64
-// GFX1250: v_ceil_f64_e32 v[254:255], 0.15915494309189532 ; encoding: [0xf8,0x30,0xfc,0x7f]
-
-// using INV2PI produces a different result
 v_ceil_f64 v[254:255], INV2PI
-// GFX1250: v_ceil_f64_e32 v[254:255], lit64(0x3fc45f306725feed) ; encoding: [0xfe,0x30,0xfc,0x7f,0xed,0xfe,0x25,0x67,0x30,0x5f,0xc4,0x3f]
+// GFX1250: v_ceil_f64_e32 v[254:255], 0.15915494309189532 ; encoding: [0xf8,0x30,0xfc,0x7f]
 
 v_ceil_f64 v[254:255], -4.0
 // GFX1250: v_ceil_f64_e32 v[254:255], -4.0         ; encoding: [0xf7,0x30,0xfc,0x7f]

llvm/test/MC/AMDGPU/gfx7_err_pos.s

@@ -42,11 +42,6 @@ v_and_b32_e64 v0, INV2PI, v1
 // CHECK-NEXT:{{^}}v_and_b32_e64 v0, INV2PI, v1
 // CHECK-NEXT:{{^}}                  ^
 
-v_and_b32_e64 v0, INV2PI64, v1
-// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: literal operands are not supported
-// CHECK-NEXT:{{^}}v_and_b32_e64 v0, INV2PI64, v1
-// CHECK-NEXT:{{^}}                  ^
-
 //==============================================================================
 // cache policy is not supported for SMRD instructions
 

llvm/test/MC/AMDGPU/literals.s

@@ -1030,7 +1030,7 @@ v_trunc_f32 v0, lit(0.159154943091895317852646485335)
 
 // SICI: v_trunc_f32_e32 v0, 0x3e22f983 ; encoding: [0xff,0x42,0x00,0x7e,0x83,0xf9,0x22,0x3e]
 // GFX89: v_trunc_f32_e32 v0, 0.15915494 ; encoding: [0xf8,0x38,0x00,0x7e]
-v_trunc_f32 v0, INV2PI64
+v_trunc_f32 v0, INV2PI
 
 //---------------------------------------------------------------------------//
 // integer literal truncation checks

llvm/test/MC/AMDGPU/literalv216-err.s

@@ -16,9 +16,6 @@ v_pk_add_f16 v1, -0.15915494, v2
 v_pk_add_f16 v1, -INV2PI, v2
 // GFX9: :[[@LINE-1]]:{{[0-9]+}}: error: literal operands are not supported
 
-v_pk_add_f16 v1, -INV2PI64, v2
-// GFX9: :[[@LINE-1]]:{{[0-9]+}}: error: literal operands are not supported
-
 v_pk_add_f16 v1, -0.0, v2
 // GFX9: :[[@LINE-1]]:{{[0-9]+}}: error: literal operands are not supported