AVR

Author: s-barannikov

llvm/lib/Target/AVR/AVRISelLowering.cpp

@@ -220,40 +220,6 @@ AVRTargetLowering::AVRTargetLowering(const AVRTargetMachine &TM,
   setMinimumJumpTableEntries(UINT_MAX);
 }
 
-const char *AVRTargetLowering::getTargetNodeName(unsigned Opcode) const {
-#define NODE(name)                                                             \
-  case AVRISD::name:                                                           \
-    return #name
-
-  switch (Opcode) {
-  default:
-    return nullptr;
-    NODE(RET_GLUE);
-    NODE(RETI_GLUE);
-    NODE(CALL);
-    NODE(WRAPPER);
-    NODE(LSL);
-    NODE(LSLW);
-    NODE(LSR);
-    NODE(LSRW);
-    NODE(ROL);
-    NODE(ROR);
-    NODE(ASR);
-    NODE(ASRW);
-    NODE(LSLLOOP);
-    NODE(LSRLOOP);
-    NODE(ROLLOOP);
-    NODE(RORLOOP);
-    NODE(ASRLOOP);
-    NODE(BRCOND);
-    NODE(CMP);
-    NODE(CMPC);
-    NODE(TST);
-    NODE(SELECT_CC);
-#undef NODE
-  }
-}
-
 EVT AVRTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
                                           EVT VT) const {
   assert(!VT.isVector() && "No AVR SetCC type for vectors!");

llvm/lib/Target/AVR/AVRISelLowering.h

@@ -19,64 +19,6 @@
 
 namespace llvm {
 
-namespace AVRISD {
-
-/// AVR Specific DAG Nodes
-enum NodeType {
-  /// Start the numbering where the builtin ops leave off.
-  FIRST_NUMBER = ISD::BUILTIN_OP_END,
-  /// Return from subroutine.
-  RET_GLUE,
-  /// Return from ISR.
-  RETI_GLUE,
-  /// Represents an abstract call instruction,
-  /// which includes a bunch of information.
-  CALL,
-  /// A wrapper node for TargetConstantPool,
-  /// TargetExternalSymbol, and TargetGlobalAddress.
-  WRAPPER,
-  LSL,     ///< Logical shift left.
-  LSLBN,   ///< Byte logical shift left N bits.
-  LSLWN,   ///< Word logical shift left N bits.
-  LSLHI,   ///< Higher 8-bit of word logical shift left.
-  LSLW,    ///< Wide logical shift left.
-  LSR,     ///< Logical shift right.
-  LSRBN,   ///< Byte logical shift right N bits.
-  LSRWN,   ///< Word logical shift right N bits.
-  LSRLO,   ///< Lower 8-bit of word logical shift right.
-  LSRW,    ///< Wide logical shift right.
-  ASR,     ///< Arithmetic shift right.
-  ASRBN,   ///< Byte arithmetic shift right N bits.
-  ASRWN,   ///< Word arithmetic shift right N bits.
-  ASRLO,   ///< Lower 8-bit of word arithmetic shift right.
-  ASRW,    ///< Wide arithmetic shift right.
-  ROR,     ///< Bit rotate right.
-  ROL,     ///< Bit rotate left.
-  LSLLOOP, ///< A loop of single logical shift left instructions.
-  LSRLOOP, ///< A loop of single logical shift right instructions.
-  ROLLOOP, ///< A loop of single left bit rotate instructions.
-  RORLOOP, ///< A loop of single right bit rotate instructions.
-  ASRLOOP, ///< A loop of single arithmetic shift right instructions.
-  /// AVR conditional branches. Operand 0 is the chain operand, operand 1
-  /// is the block to branch if condition is true, operand 2 is the
-  /// condition code, and operand 3 is the flag operand produced by a CMP
-  /// or TEST instruction.
-  BRCOND,
-  /// Compare instruction.
-  CMP,
-  /// Compare with carry instruction.
-  CMPC,
-  /// Test for zero or minus instruction.
-  TST,
-  /// Swap Rd[7:4] <-> Rd[3:0].
-  SWAP,
-  /// Operand 0 and operand 1 are selection variable, operand 2
-  /// is condition code and operand 3 is flag operand.
-  SELECT_CC
-};
-
-} // end of namespace AVRISD
-
 class AVRSubtarget;
 class AVRTargetMachine;
 
@@ -95,8 +37,6 @@ class AVRTargetLowering : public TargetLowering {
     return MVT::i8;
   }
 
-  const char *getTargetNodeName(unsigned Opcode) const override;
-
   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
 
   void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,

llvm/lib/Target/AVR/AVRSelectionDAGInfo.cpp

@@ -0,0 +1,19 @@
+//===- AVRSelectionDAGInfo.cpp --------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "AVRSelectionDAGInfo.h"
+
+#define GET_SDNODE_DESC
+#include "AVRGenSDNodeInfo.inc"
+
+using namespace llvm;
+
+AVRSelectionDAGInfo::AVRSelectionDAGInfo()
+    : SelectionDAGGenTargetInfo(AVRGenSDNodeInfo) {}
+
+AVRSelectionDAGInfo::~AVRSelectionDAGInfo() = default;

llvm/lib/Target/AVR/AVRSelectionDAGInfo.h

@@ -15,11 +15,17 @@
 
 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
 
+#define GET_SDNODE_ENUM
+#include "AVRGenSDNodeInfo.inc"
+
 namespace llvm {
 
 /// Holds information about the AVR instruction selection DAG.
-class AVRSelectionDAGInfo : public SelectionDAGTargetInfo {
+class AVRSelectionDAGInfo : public SelectionDAGGenTargetInfo {
 public:
+  AVRSelectionDAGInfo();
+
+  ~AVRSelectionDAGInfo() override;
 };
 
 } // end namespace llvm

llvm/lib/Target/AVR/CMakeLists.txt

@@ -10,6 +10,7 @@ tablegen(LLVM AVRGenDisassemblerTables.inc -gen-disassembler)
 tablegen(LLVM AVRGenInstrInfo.inc -gen-instr-info)
 tablegen(LLVM AVRGenMCCodeEmitter.inc -gen-emitter)
 tablegen(LLVM AVRGenRegisterInfo.inc -gen-register-info)
+tablegen(LLVM AVRGenSDNodeInfo.inc -gen-sd-node-info)
 tablegen(LLVM AVRGenSubtargetInfo.inc -gen-subtarget)
 
 add_public_tablegen_target(AVRCommonTableGen)
@@ -23,6 +24,7 @@ add_llvm_target(AVRCodeGen
   AVRISelLowering.cpp
   AVRMCInstLower.cpp
   AVRRegisterInfo.cpp
+  AVRSelectionDAGInfo.cpp
   AVRShiftExpand.cpp
   AVRSubtarget.cpp
   AVRTargetMachine.cpp