We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
1 parent 8df283b commit 3bfff33Copy full SHA for 3bfff33
llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -1510,7 +1510,7 @@ RISCVVLOptimizer::checkUsers(const MachineInstr &MI) const {
1510
// or another INSERT_SUBREG, since VL just works differently
1511
// between segmented operations (per-field) v.s. other RVV ops (on the
1512
// whole register group).
1513
- if (CandidateMI.getOpcode() == RISCV::INSERT_SUBREG ||
+ if (isTupleInsertInstr(CandidateMI, *MRI) ||
1514
isSegmentedStoreInstr(CandidateMI))
1515
Worklist.insert(&UseOp);
1516
}
0 commit comments