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[AMDGPU][MC] Do not inline lit()/lit64() operands.
For now treat the modifiers synonymous to each other. The disassembler side is to be addressed separately.
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5 files changed

+435
-82
lines changed

5 files changed

+435
-82
lines changed

‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp‎

Lines changed: 34 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -2097,6 +2097,10 @@ bool AMDGPUOperand::isInlinableImm(MVT type) const {
20972097
// Only plain immediates are inlinable (e.g. "clamp" attribute is not)
20982098
return false;
20992099
}
2100+
2101+
if (getModifiers().Lit != LitModifier::None)
2102+
return false;
2103+
21002104
// TODO: We should avoid using host float here. It would be better to
21012105
// check the float bit values which is what a few other places do.
21022106
// We've had bot failures before due to weird NaN support on mips hosts.
@@ -2341,7 +2345,8 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
23412345
case AMDGPU::OPERAND_REG_INLINE_C_INT64:
23422346
case AMDGPU::OPERAND_REG_INLINE_C_FP64:
23432347
case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
2344-
if (AMDGPU::isInlinableLiteral64(Literal.getZExtValue(),
2348+
if (Lit == LitModifier::None &&
2349+
AMDGPU::isInlinableLiteral64(Literal.getZExtValue(),
23452350
AsmParser->hasInv2PiInlineImm())) {
23462351
Inst.addOperand(MCOperand::createImm(Literal.getZExtValue()));
23472352
return;
@@ -2378,14 +2383,7 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
23782383
Val = Hi_32(Val);
23792384
}
23802385
}
2381-
2382-
if (Lit != LitModifier::None) {
2383-
Inst.addOperand(
2384-
MCOperand::createExpr(AMDGPUMCExpr::createLit(Lit, Val, Ctx)));
2385-
} else {
2386-
Inst.addOperand(MCOperand::createImm(Val));
2387-
}
2388-
return;
2386+
break;
23892387
}
23902388

23912389
// We don't allow fp literals in 64-bit integer instructions. It is
@@ -2397,20 +2395,14 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
23972395
if (CanUse64BitLiterals && Lit == LitModifier::None &&
23982396
(isInt<32>(Val) || isUInt<32>(Val)))
23992397
Lit = LitModifier::Lit64;
2400-
2401-
if (Lit != LitModifier::None) {
2402-
Inst.addOperand(
2403-
MCOperand::createExpr(AMDGPUMCExpr::createLit(Lit, Val, Ctx)));
2404-
} else {
2405-
Inst.addOperand(MCOperand::createImm(Val));
2406-
}
2407-
return;
2398+
break;
24082399

24092400
case AMDGPU::OPERAND_REG_IMM_BF16:
24102401
case AMDGPU::OPERAND_REG_INLINE_C_BF16:
24112402
case AMDGPU::OPERAND_REG_INLINE_C_V2BF16:
24122403
case AMDGPU::OPERAND_REG_IMM_V2BF16:
2413-
if (AsmParser->hasInv2PiInlineImm() && Literal == 0x3fc45f306725feed) {
2404+
if (Lit == LitModifier::None && AsmParser->hasInv2PiInlineImm() &&
2405+
Literal == 0x3fc45f306725feed) {
24142406
// This is the 1/(2*pi) which is going to be truncated to bf16 with the
24152407
// loss of precision. The constant represents ideomatic fp32 value of
24162408
// 1/(2*pi) = 0.15915494 since bf16 is in fact fp32 with cleared low 16
@@ -2448,14 +2440,19 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
24482440
// We allow precision lost but not overflow or underflow. This should be
24492441
// checked earlier in isLiteralImm()
24502442

2451-
uint64_t ImmVal = FPLiteral.bitcastToAPInt().getZExtValue();
2452-
Inst.addOperand(MCOperand::createImm(ImmVal));
2453-
return;
2443+
Val = FPLiteral.bitcastToAPInt().getZExtValue();
2444+
break;
24542445
}
24552446
default:
24562447
llvm_unreachable("invalid operand size");
24572448
}
24582449

2450+
if (Lit != LitModifier::None) {
2451+
Inst.addOperand(
2452+
MCOperand::createExpr(AMDGPUMCExpr::createLit(Lit, Val, Ctx)));
2453+
} else {
2454+
Inst.addOperand(MCOperand::createImm(Val));
2455+
}
24592456
return;
24602457
}
24612458

@@ -2475,12 +2472,12 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
24752472
case AMDGPU::OPERAND_REG_IMM_V2INT32:
24762473
case AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32:
24772474
case AMDGPU::OPERAND_REG_IMM_NOINLINE_V2FP16:
2478-
Inst.addOperand(MCOperand::createImm(Val));
2479-
return;
2475+
break;
24802476

24812477
case AMDGPU::OPERAND_REG_IMM_INT64:
24822478
case AMDGPU::OPERAND_REG_INLINE_C_INT64:
2483-
if (AMDGPU::isInlinableLiteral64(Val, AsmParser->hasInv2PiInlineImm())) {
2479+
if (Lit == LitModifier::None &&
2480+
AMDGPU::isInlinableLiteral64(Val, AsmParser->hasInv2PiInlineImm())) {
24842481
Inst.addOperand(MCOperand::createImm(Val));
24852482
return;
24862483
}
@@ -2491,19 +2488,13 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
24912488
// LSBs.
24922489
if (!AsmParser->has64BitLiterals() || Lit == LitModifier::Lit)
24932490
Val = Lo_32(Val);
2494-
2495-
if (Lit != LitModifier::None) {
2496-
Inst.addOperand(
2497-
MCOperand::createExpr(AMDGPUMCExpr::createLit(Lit, Val, Ctx)));
2498-
} else {
2499-
Inst.addOperand(MCOperand::createImm(Val));
2500-
}
2501-
return;
2491+
break;
25022492

25032493
case AMDGPU::OPERAND_REG_IMM_FP64:
25042494
case AMDGPU::OPERAND_REG_INLINE_C_FP64:
25052495
case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
2506-
if (AMDGPU::isInlinableLiteral64(Val, AsmParser->hasInv2PiInlineImm())) {
2496+
if (Lit == LitModifier::None &&
2497+
AMDGPU::isInlinableLiteral64(Val, AsmParser->hasInv2PiInlineImm())) {
25072498
Inst.addOperand(MCOperand::createImm(Val));
25082499
return;
25092500
}
@@ -2526,14 +2517,7 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
25262517
// For FP64 operands lit() specifies the high half of the value.
25272518
if (Lit == LitModifier::Lit)
25282519
Val = Hi_32(Val);
2529-
2530-
if (Lit != LitModifier::None) {
2531-
Inst.addOperand(
2532-
MCOperand::createExpr(AMDGPUMCExpr::createLit(Lit, Val, Ctx)));
2533-
} else {
2534-
Inst.addOperand(MCOperand::createImm(Val));
2535-
}
2536-
return;
2520+
break;
25372521

25382522
case AMDGPU::OPERAND_REG_IMM_INT16:
25392523
case AMDGPU::OPERAND_REG_INLINE_C_INT16:
@@ -2546,24 +2530,23 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
25462530
case AMDGPU::OPERAND_REG_INLINE_C_V2BF16:
25472531
case AMDGPU::OPERAND_KIMM32:
25482532
case AMDGPU::OPERAND_KIMM16:
2549-
Inst.addOperand(MCOperand::createImm(Val));
2550-
return;
2533+
break;
25512534

25522535
case AMDGPU::OPERAND_KIMM64:
25532536
if ((isInt<32>(Val) || isUInt<32>(Val)) && Lit != LitModifier::Lit64)
25542537
Val <<= 32;
2555-
2556-
if (Lit != LitModifier::None) {
2557-
Inst.addOperand(
2558-
MCOperand::createExpr(AMDGPUMCExpr::createLit(Lit, Val, Ctx)));
2559-
} else {
2560-
Inst.addOperand(MCOperand::createImm(Val));
2561-
}
2562-
return;
2538+
break;
25632539

25642540
default:
25652541
llvm_unreachable("invalid operand type");
25662542
}
2543+
2544+
if (Lit != LitModifier::None) {
2545+
Inst.addOperand(
2546+
MCOperand::createExpr(AMDGPUMCExpr::createLit(Lit, Val, Ctx)));
2547+
} else {
2548+
Inst.addOperand(MCOperand::createImm(Val));
2549+
}
25672550
}
25682551

25692552
void AMDGPUOperand::addRegOperands(MCInst &Inst, unsigned N) const {

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp‎

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -73,7 +73,13 @@ void AMDGPUInstPrinter::printU16ImmDecOperand(const MCInst *MI, unsigned OpNo,
7373
void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo,
7474
const MCSubtargetInfo &STI,
7575
raw_ostream &O) {
76-
O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff);
76+
const MCOperand &Op = MI->getOperand(OpNo);
77+
if (Op.isExpr()) {
78+
MAI.printExpr(O, *Op.getExpr());
79+
return;
80+
}
81+
82+
O << formatHex(Op.getImm() & 0xffffffff);
7783
}
7884

7985
void AMDGPUInstPrinter::printFP64ImmOperand(const MCInst *MI, unsigned OpNo,

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp‎

Lines changed: 12 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -270,10 +270,19 @@ std::optional<uint64_t> AMDGPUMCCodeEmitter::getLitEncoding(
270270
const MCInstrDesc &Desc, const MCOperand &MO, unsigned OpNo,
271271
const MCSubtargetInfo &STI, bool HasMandatoryLiteral) const {
272272
const MCOperandInfo &OpInfo = Desc.operands()[OpNo];
273-
int64_t Imm;
273+
int64_t Imm = 0;
274274
if (MO.isExpr()) {
275-
if (!MO.getExpr()->evaluateAsAbsolute(Imm))
276-
return AMDGPU::getOperandSize(OpInfo) == 8 ? 254 : 255;
275+
if (!MO.getExpr()->evaluateAsAbsolute(Imm) ||
276+
AMDGPU::isLitExpr(MO.getExpr())) {
277+
if (OpInfo.OperandType == AMDGPU::OPERAND_KIMM16 ||
278+
OpInfo.OperandType == AMDGPU::OPERAND_KIMM32 ||
279+
OpInfo.OperandType == AMDGPU::OPERAND_KIMM64)
280+
return Imm;
281+
if (STI.hasFeature(AMDGPU::Feature64BitLiterals) &&
282+
AMDGPU::getOperandSize(OpInfo) == 8)
283+
return 254;
284+
return 255;
285+
}
277286
} else {
278287
assert(!MO.isDFPImm());
279288

‎llvm/test/MC/AMDGPU/gfx1250_asm_salu_lit64.s‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -62,8 +62,9 @@ s_cselect_b64 s[2:3], s[4:5], 0x10abcdef12345678
6262
s_mov_b64 s[2:3], 0xffffffff01234567
6363
// GFX1250: s_mov_b64 s[2:3], 0xffffffff01234567 ; encoding: [0xfe,0x01,0x82,0xbe,0x67,0x45,0x23,0x01,0xff,0xff,0xff,0xff]
6464

65+
// TODO: disasm
6566
s_mov_b64 s[2:3], lit64(0x777)
66-
// GFX1250-ASM: s_mov_b64 s[2:3], lit64(0x777) ; encoding: [0xff,0x01,0x82,0xbe,0x77,0x07,0x00,0x00]
67+
// GFX1250-ASM: s_mov_b64 s[2:3], lit64(0x777) ; encoding: [0xfe,0x01,0x82,0xbe,0x77,0x07,0x00,0x00,0x00,0x00,0x00,0x00]
6768
// GFX1250-DIS: s_mov_b64 s[2:3], 0x777 ; encoding: [0xff,0x01,0x82,0xbe,0x77,0x07,0x00,0x00]
6869

6970
s_mov_b64 s[2:3], 0x777

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