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[AMDGPU] Ignore inactive VGPRs in .vgpr_count
When using the `amdgcn.init.whole.wave` intrinsic, we add dummy VGPR arguments with the purpose of preserving their inactive lanes. The pattern may look something like this: ``` entry: call amdgcn.init.whole.wave branch to shader or tail shader: $vInactive = IMPLICIT_DEF ; Tells regalloc it's safe to use the active lanes actual code... tail: call amdgcn.cs.chain [...], implicit $vInactive ``` We should not report these VGPRs in the `.vgpr_count` metadata. This patch achieves that goal by ignoring IMPLICIT_DEFs and calls. This should be safe since if those registers are actually used in any other context, they will be counted there. It also reduces the scope of the code that counts unused function arguments to only work on entry functions, since only they need to handle hardware-initialized registers. This is a reworked version of #133242, which was reverted in #144039.
1 parent 1ea0b5b commit 3ccfa1e

12 files changed

+390
-4
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -993,7 +993,7 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
993993
// dispatch registers are function args.
994994
unsigned WaveDispatchNumSGPR = 0, WaveDispatchNumVGPR = 0;
995995

996-
if (isShader(F.getCallingConv())) {
996+
if (AMDGPU::shouldReportUnusedFuncArgs(F.getCallingConv())) {
997997
bool IsPixelShader =
998998
F.getCallingConv() == CallingConv::AMDGPU_PS && !STM.isAmdHsaOS();
999999

‎llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.cpp‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -213,6 +213,9 @@ AMDGPUResourceUsageAnalysis::analyzeResourceUsage(
213213
if (!RC || !TRI.isVGPRClass(RC))
214214
continue;
215215

216+
if (MI.isCall() || MI.isImplicitDef())
217+
continue;
218+
216219
unsigned Width = divideCeil(TRI.getRegSizeInBits(*RC), 32);
217220
unsigned HWReg = TRI.getHWRegIndex(Reg);
218221
int MaxUsed = HWReg + Width - 1;

‎llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h‎

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1367,6 +1367,28 @@ constexpr bool isEntryFunctionCC(CallingConv::ID CC) {
13671367
}
13681368
}
13691369

1370+
// Shaders that are entry functions need to count input arguments even if
1371+
// they're not used (i.e. not reported by AMDGPUResourceUsageAnalysis). Other
1372+
// functions can skip including them. This is especially important for shaders
1373+
// that use the init.whole.wave intrinsic, since they sometimes have VGPR
1374+
// arguments that are only added for the purpose of preserving their inactive
1375+
// lanes and should not be included in the vgpr-count.
1376+
LLVM_READNONE
1377+
constexpr bool shouldReportUnusedFuncArgs(CallingConv::ID CC) {
1378+
switch (CC) {
1379+
case CallingConv::AMDGPU_VS:
1380+
case CallingConv::AMDGPU_LS:
1381+
case CallingConv::AMDGPU_HS:
1382+
case CallingConv::AMDGPU_ES:
1383+
case CallingConv::AMDGPU_GS:
1384+
case CallingConv::AMDGPU_PS:
1385+
case CallingConv::AMDGPU_CS:
1386+
return true;
1387+
default:
1388+
return false;
1389+
}
1390+
}
1391+
13701392
LLVM_READNONE
13711393
constexpr bool isChainCC(CallingConv::ID CC) {
13721394
switch (CC) {

‎llvm/test/CodeGen/AMDGPU/init-whole-wave-vgpr-count-large.ll‎

Lines changed: 76 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,76 @@
1+
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1200 < %s | FileCheck %s
2+
3+
; CHECK-LABEL: .shader_functions:
4+
5+
; Use VGPRs above the input arguments.
6+
; CHECK-LABEL: _miss_1:
7+
; CHECK: .vgpr_count:{{.*}}0x1d{{$}}
8+
9+
define amdgpu_cs_chain void @_miss_1(ptr inreg %next.callee, i32 inreg %global.table, i32 inreg %max.outgoing.vgpr.count,
10+
i32 %vcr, { i32 } %system.data,
11+
i32 %inactive.vgpr, i32 %inactive.vgpr1, i32 %inactive.vgpr2, i32 %inactive.vgpr3,
12+
i32 %inactive.vgpr4, i32 %inactive.vgpr5, i32 %inactive.vgpr6, i32 %inactive.vgpr7,
13+
i32 %inactive.vgpr8, i32 %inactive.vgpr9)
14+
local_unnamed_addr {
15+
entry:
16+
%system.data.value = extractvalue { i32 } %system.data, 0
17+
%dead.val = call i32 @llvm.amdgcn.dead.i32()
18+
%is.whole.wave = call i1 @llvm.amdgcn.init.whole.wave()
19+
br i1 %is.whole.wave, label %shader, label %tail
20+
21+
shader:
22+
%system.data.extract = extractvalue { i32 } %system.data, 0
23+
%data.mul = mul i32 %system.data.extract, 2
24+
%data.add = add i32 %data.mul, 1
25+
call void asm sideeffect "; clobber v28", "~{v28}"()
26+
br label %tail
27+
28+
tail:
29+
%final.vcr = phi i32 [ %vcr, %entry ], [ %data.mul, %shader ]
30+
%final.sys.data = phi i32 [ %system.data.value, %entry ], [ %data.add, %shader ]
31+
%final.inactive0 = phi i32 [ %inactive.vgpr, %entry ], [ %dead.val, %shader ]
32+
%final.inactive1 = phi i32 [ %inactive.vgpr1, %entry ], [ %dead.val, %shader ]
33+
%final.inactive2 = phi i32 [ %inactive.vgpr2, %entry ], [ %dead.val, %shader ]
34+
%final.inactive3 = phi i32 [ %inactive.vgpr3, %entry ], [ %dead.val, %shader ]
35+
%final.inactive4 = phi i32 [ %inactive.vgpr4, %entry ], [ %dead.val, %shader ]
36+
%final.inactive5 = phi i32 [ %inactive.vgpr5, %entry ], [ %dead.val, %shader ]
37+
%final.inactive6 = phi i32 [ %inactive.vgpr6, %entry ], [ %dead.val, %shader ]
38+
%final.inactive7 = phi i32 [ %inactive.vgpr7, %entry ], [ %dead.val, %shader ]
39+
%final.inactive8 = phi i32 [ %inactive.vgpr8, %entry ], [ %dead.val, %shader ]
40+
%final.inactive9 = phi i32 [ %inactive.vgpr9, %entry ], [ %dead.val, %shader ]
41+
42+
%struct.init = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } poison, i32 %final.vcr, 0
43+
%struct.with.data = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %struct.init, i32 %final.sys.data, 1
44+
%struct.with.inactive0 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %struct.with.data, i32 %final.inactive0, 2
45+
%struct.with.inactive1 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %struct.with.inactive0, i32 %final.inactive1, 3
46+
%struct.with.inactive2 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %struct.with.inactive1, i32 %final.inactive2, 4
47+
%struct.with.inactive3 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %struct.with.inactive2, i32 %final.inactive3, 5
48+
%struct.with.inactive4 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %struct.with.inactive3, i32 %final.inactive4, 6
49+
%struct.with.inactive5 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %struct.with.inactive4, i32 %final.inactive5, 7
50+
%struct.with.inactive6 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %struct.with.inactive5, i32 %final.inactive6, 8
51+
%struct.with.inactive7 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %struct.with.inactive6, i32 %final.inactive7, 9
52+
%struct.with.inactive8 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %struct.with.inactive7, i32 %final.inactive8, 10
53+
%final.struct = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %struct.with.inactive8, i32 %final.inactive9, 11
54+
55+
%vec.global = insertelement <4 x i32> poison, i32 %global.table, i64 0
56+
%vec.max.vgpr = insertelement <4 x i32> %vec.global, i32 %max.outgoing.vgpr.count, i64 1
57+
%vec.sys.data = insertelement <4 x i32> %vec.max.vgpr, i32 %final.sys.data, i64 2
58+
%final.vec = insertelement <4 x i32> %vec.sys.data, i32 0, i64 3
59+
60+
call void (ptr, i32, <4 x i32>, { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }, i32, ...)
61+
@llvm.amdgcn.cs.chain.p0.i32.v4i32.sl_i32i32i32i32i32i32i32i32i32i32i32i32s(
62+
ptr %next.callee, i32 0, <4 x i32> inreg %final.vec,
63+
{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %final.struct,
64+
i32 1, i32 %max.outgoing.vgpr.count, i32 -1, ptr @retry_vgpr_alloc.v4i32)
65+
unreachable
66+
}
67+
68+
declare i32 @llvm.amdgcn.dead.i32()
69+
declare i1 @llvm.amdgcn.init.whole.wave()
70+
declare void @llvm.amdgcn.cs.chain.p0.i32.v4i32.sl_i32i32i32i32i32i32i32i32i32i32i32i32s(ptr, i32, <4 x i32>, { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }, i32 immarg, ...)
71+
72+
declare amdgpu_cs_chain void @retry_vgpr_alloc.v4i32(<4 x i32> inreg)
73+
74+
!amdgpu.pal.metadata.msgpack = !{!0}
75+
76+
!0 = !{!"\82\B0amdpal.pipelines\91\8B\A4.api\A6Vulkan\B2.compute_registers\85\AB.tg_size_en\C3\AA.tgid_x_en\C3\AA.tgid_y_en\C3\AA.tgid_z_en\C3\AF.tidig_comp_cnt\00\B0.hardware_stages\81\A3.cs\8D\AF.checksum_value\00\AB.debug_mode\00\AB.float_mode\CC\C0\A9.image_op\C2\AC.mem_ordered\C3\AB.sgpr_limitj\B7.threadgroup_dimensions\93 \01\01\AD.trap_present\00\B2.user_data_reg_map\90\AB.user_sgprs\10\AB.vgpr_limit\CD\01\00\AF.wavefront_size \AF.wg_round_robin\C2\B7.internal_pipeline_hash\92\CF|{2&\DCC\85M\CFep\8A\EDR\DE\D6\E1\B1.shader_functions\81\A7_miss_1\82\B4.frontend_stack_size\00\B4.outgoing_vgpr_countP\A8.shaders\81\A8.compute\82\B0.api_shader_hash\92\00\00\B1.hardware_mapping\91\A3.cs\B0.spill_threshold\CD\FF\FF\A5.type\A2Cs\B0.user_data_limit\01\A9.uses_cps\C3\AF.xgl_cache_info\82\B3.128_bit_cache_hash\92\CF\B4\AF\9D\0B\07\88\03\02\CF\01o\C9\CAf?)\DA\AD.llpc_version\A476.0\AEamdpal.version\92\03\00"}

‎llvm/test/CodeGen/AMDGPU/init-whole-wave-vgpr-count-leaf.ll‎

Lines changed: 50 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,50 @@
1+
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1200 < %s | FileCheck %s
2+
3+
; CHECK-LABEL: .shader_functions:
4+
5+
; Make sure that .vgpr_count doesn't include the %inactive.vgpr registers.
6+
; CHECK-LABEL: leaf_shader:
7+
; CHECK: .vgpr_count:{{.*}}0xc{{$}}
8+
9+
; Function without calls.
10+
define amdgpu_cs_chain void @_leaf_shader(ptr %output.ptr, i32 inreg %input.value,
11+
i32 %active.vgpr1, i32 %active.vgpr2,
12+
i32 %inactive.vgpr1, i32 %inactive.vgpr2, i32 %inactive.vgpr3,
13+
i32 %inactive.vgpr4, i32 %inactive.vgpr5, i32 %inactive.vgpr6)
14+
local_unnamed_addr {
15+
entry:
16+
%dead.val = call i32 @llvm.amdgcn.dead.i32()
17+
%is.whole.wave = call i1 @llvm.amdgcn.init.whole.wave()
18+
br i1 %is.whole.wave, label %compute, label %merge
19+
20+
compute:
21+
; Perform a more complex computation using active VGPRs
22+
%square = mul i32 %active.vgpr1, %active.vgpr1
23+
%product = mul i32 %square, %active.vgpr2
24+
%sum = add i32 %product, %input.value
25+
%result = add i32 %sum, 42
26+
br label %merge
27+
28+
merge:
29+
%final.result = phi i32 [ 0, %entry ], [ %result, %compute ]
30+
%final.inactive1 = phi i32 [ %inactive.vgpr1, %entry ], [ %dead.val, %compute ]
31+
%final.inactive2 = phi i32 [ %inactive.vgpr2, %entry ], [ %dead.val, %compute ]
32+
%final.inactive3 = phi i32 [ %inactive.vgpr3, %entry ], [ %dead.val, %compute ]
33+
%final.inactive4 = phi i32 [ %inactive.vgpr4, %entry ], [ %dead.val, %compute ]
34+
%final.inactive5 = phi i32 [ %inactive.vgpr5, %entry ], [ %dead.val, %compute ]
35+
%final.inactive6 = phi i32 [ %inactive.vgpr6, %entry ], [ %dead.val, %compute ]
36+
37+
store i32 %final.result, ptr %output.ptr, align 4
38+
39+
ret void
40+
}
41+
42+
declare i32 @llvm.amdgcn.dead.i32()
43+
declare i1 @llvm.amdgcn.init.whole.wave()
44+
declare void @llvm.amdgcn.cs.chain.p0.i32.v4i32.sl_i32i32i32i32i32i32i32i32i32i32i32i32s(ptr, i32, <4 x i32>, { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }, i32 immarg, ...)
45+
46+
declare amdgpu_cs_chain void @retry_vgpr_alloc.v4i32(<4 x i32> inreg)
47+
48+
!amdgpu.pal.metadata.msgpack = !{!0}
49+
50+
!0 = !{!"\82\B0amdpal.pipelines\91\8B\A4.api\A6Vulkan\B2.compute_registers\85\AB.tg_size_en\C3\AA.tgid_x_en\C3\AA.tgid_y_en\C3\AA.tgid_z_en\C3\AF.tidig_comp_cnt\00\B0.hardware_stages\81\A3.cs\8D\AF.checksum_value\00\AB.debug_mode\00\AB.float_mode\CC\C0\A9.image_op\C2\AC.mem_ordered\C3\AB.sgpr_limitj\B7.threadgroup_dimensions\93 \01\01\AD.trap_present\00\B2.user_data_reg_map\90\AB.user_sgprs\10\AB.vgpr_limit\CD\01\00\AF.wavefront_size \AF.wg_round_robin\C2\B7.internal_pipeline_hash\92\CF|{2&\DCC\85M\CFep\8A\EDR\DE\D6\E1\B1.shader_functions\81\A7_miss_1\82\B4.frontend_stack_size\00\B4.outgoing_vgpr_countP\A8.shaders\81\A8.compute\82\B0.api_shader_hash\92\00\00\B1.hardware_mapping\91\A3.cs\B0.spill_threshold\CD\FF\FF\A5.type\A2Cs\B0.user_data_limit\01\A9.uses_cps\C3\AF.xgl_cache_info\82\B3.128_bit_cache_hash\92\CF\B4\AF\9D\0B\07\88\03\02\CF\01o\C9\CAf?)\DA\AD.llpc_version\A476.0\AEamdpal.version\92\03\00"}

‎llvm/test/CodeGen/AMDGPU/init-whole-wave-vgpr-count-use-inactive.ll‎

Lines changed: 78 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,78 @@
1+
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1200 < %s | FileCheck %s
2+
3+
; CHECK-LABEL: .shader_functions:
4+
5+
; Make sure that .vgpr_count doesn't include the %inactive.vgpr registers.
6+
; The shader is free to use any of the VGPRs mapped to a %inactive.vgpr as long as it only touches its active lanes.
7+
; In that case, the VGPR should be included in the .vgpr_count
8+
; CHECK-LABEL: _miss_1:
9+
; CHECK: .vgpr_count:{{.*}}0xd{{$}}
10+
11+
define amdgpu_cs_chain void @_miss_1(ptr inreg %next.callee, i32 inreg %global.table, i32 inreg %max.outgoing.vgpr.count,
12+
i32 %vcr, { i32 } %system.data,
13+
i32 %inactive.vgpr, i32 %inactive.vgpr1, i32 %inactive.vgpr2, i32 %inactive.vgpr3,
14+
i32 %inactive.vgpr4, i32 %inactive.vgpr5, i32 %inactive.vgpr6, i32 %inactive.vgpr7,
15+
i32 %inactive.vgpr8, i32 %inactive.vgpr9)
16+
local_unnamed_addr {
17+
entry:
18+
%system.data.value = extractvalue { i32 } %system.data, 0
19+
%dead.val = call i32 @llvm.amdgcn.dead.i32()
20+
%is.whole.wave = call i1 @llvm.amdgcn.init.whole.wave()
21+
br i1 %is.whole.wave, label %shader, label %tail
22+
23+
shader:
24+
%system.data.extract = extractvalue { i32 } %system.data, 0
25+
%data.mul = mul i32 %system.data.extract, 2
26+
%data.add = add i32 %data.mul, 1
27+
call void asm sideeffect "; use VGPR for %inactive.vgpr2", "~{v12}"()
28+
br label %tail
29+
30+
tail:
31+
%final.vcr = phi i32 [ %vcr, %entry ], [ %data.mul, %shader ]
32+
%final.sys.data = phi i32 [ %system.data.value, %entry ], [ %data.add, %shader ]
33+
%final.inactive0 = phi i32 [ %inactive.vgpr, %entry ], [ %dead.val, %shader ]
34+
%final.inactive1 = phi i32 [ %inactive.vgpr1, %entry ], [ %dead.val, %shader ]
35+
%final.inactive2 = phi i32 [ %inactive.vgpr2, %entry ], [ %dead.val, %shader ]
36+
%final.inactive3 = phi i32 [ %inactive.vgpr3, %entry ], [ %dead.val, %shader ]
37+
%final.inactive4 = phi i32 [ %inactive.vgpr4, %entry ], [ %dead.val, %shader ]
38+
%final.inactive5 = phi i32 [ %inactive.vgpr5, %entry ], [ %dead.val, %shader ]
39+
%final.inactive6 = phi i32 [ %inactive.vgpr6, %entry ], [ %dead.val, %shader ]
40+
%final.inactive7 = phi i32 [ %inactive.vgpr7, %entry ], [ %dead.val, %shader ]
41+
%final.inactive8 = phi i32 [ %inactive.vgpr8, %entry ], [ %dead.val, %shader ]
42+
%final.inactive9 = phi i32 [ %inactive.vgpr9, %entry ], [ %dead.val, %shader ]
43+
44+
%struct.init = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } poison, i32 %final.vcr, 0
45+
%struct.with.data = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %struct.init, i32 %final.sys.data, 1
46+
%struct.with.inactive0 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %struct.with.data, i32 %final.inactive0, 2
47+
%struct.with.inactive1 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %struct.with.inactive0, i32 %final.inactive1, 3
48+
%struct.with.inactive2 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %struct.with.inactive1, i32 %final.inactive2, 4
49+
%struct.with.inactive3 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %struct.with.inactive2, i32 %final.inactive3, 5
50+
%struct.with.inactive4 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %struct.with.inactive3, i32 %final.inactive4, 6
51+
%struct.with.inactive5 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %struct.with.inactive4, i32 %final.inactive5, 7
52+
%struct.with.inactive6 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %struct.with.inactive5, i32 %final.inactive6, 8
53+
%struct.with.inactive7 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %struct.with.inactive6, i32 %final.inactive7, 9
54+
%struct.with.inactive8 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %struct.with.inactive7, i32 %final.inactive8, 10
55+
%final.struct = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %struct.with.inactive8, i32 %final.inactive9, 11
56+
57+
%vec.global = insertelement <4 x i32> poison, i32 %global.table, i64 0
58+
%vec.max.vgpr = insertelement <4 x i32> %vec.global, i32 %max.outgoing.vgpr.count, i64 1
59+
%vec.sys.data = insertelement <4 x i32> %vec.max.vgpr, i32 %final.sys.data, i64 2
60+
%final.vec = insertelement <4 x i32> %vec.sys.data, i32 0, i64 3
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call void (ptr, i32, <4 x i32>, { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }, i32, ...)
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@llvm.amdgcn.cs.chain.p0.i32.v4i32.sl_i32i32i32i32i32i32i32i32i32i32i32i32s(
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ptr %next.callee, i32 0, <4 x i32> inreg %final.vec,
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{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %final.struct,
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i32 1, i32 %max.outgoing.vgpr.count, i32 -1, ptr @retry_vgpr_alloc.v4i32)
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unreachable
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}
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declare i32 @llvm.amdgcn.dead.i32()
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declare i1 @llvm.amdgcn.init.whole.wave()
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declare void @llvm.amdgcn.cs.chain.p0.i32.v4i32.sl_i32i32i32i32i32i32i32i32i32i32i32i32s(ptr, i32, <4 x i32>, { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }, i32 immarg, ...)
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declare amdgpu_cs_chain void @retry_vgpr_alloc.v4i32(<4 x i32> inreg)
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!amdgpu.pal.metadata.msgpack = !{!0}
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!0 = !{!"\82\B0amdpal.pipelines\91\8B\A4.api\A6Vulkan\B2.compute_registers\85\AB.tg_size_en\C3\AA.tgid_x_en\C3\AA.tgid_y_en\C3\AA.tgid_z_en\C3\AF.tidig_comp_cnt\00\B0.hardware_stages\81\A3.cs\8D\AF.checksum_value\00\AB.debug_mode\00\AB.float_mode\CC\C0\A9.image_op\C2\AC.mem_ordered\C3\AB.sgpr_limitj\B7.threadgroup_dimensions\93 \01\01\AD.trap_present\00\B2.user_data_reg_map\90\AB.user_sgprs\10\AB.vgpr_limit\CD\01\00\AF.wavefront_size \AF.wg_round_robin\C2\B7.internal_pipeline_hash\92\CF|{2&\DCC\85M\CFep\8A\EDR\DE\D6\E1\B1.shader_functions\81\A7_miss_1\82\B4.frontend_stack_size\00\B4.outgoing_vgpr_countP\A8.shaders\81\A8.compute\82\B0.api_shader_hash\92\00\00\B1.hardware_mapping\91\A3.cs\B0.spill_threshold\CD\FF\FF\A5.type\A2Cs\B0.user_data_limit\01\A9.uses_cps\C3\AF.xgl_cache_info\82\B3.128_bit_cache_hash\92\CF\B4\AF\9D\0B\07\88\03\02\CF\01o\C9\CAf?)\DA\AD.llpc_version\A476.0\AEamdpal.version\92\03\00"}

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