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[HLSL][SPIRV][DXIL] Implement dot4add_i8packed intrinsic (#113623)
- create a clang built-in in Builtins.td - link dot4add_i8packed in hlsl_intrinsics.h - add lowering to spirv backend through expansion of operation as OPSDot is missing up to SPIRV 1.6 in SPIRVInstructionSelector.cpp - add lowering to spirv backend using OpSDot in applicable SPIRV version or if SPV_KHR_integer_dot_product is enabled - add dot4add_i8packed intrinsic to IntrinsicsDirectX.td and mapping to DXIL.td op Dot4AddI8Packed - add tests for HLSL intrinsic lowering to dx/spv intrinsic in dot4add_i8packed.hlsl - add tests for sema checks in dot4add_i8packed-errors.hlsl - add test of spir-v lowering in SPIRV/dot4add_i8packed.ll - add test to dxil lowering in DirectX/dot4add_i8packed.ll Resolves #99220
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‎clang/include/clang/Basic/Builtins.td

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@@ -4792,6 +4792,12 @@ def HLSLDotProduct : LangBuiltin<"HLSL_LANG"> {
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let Prototype = "void(...)";
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}
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def HLSLDot4AddI8Packed : LangBuiltin<"HLSL_LANG"> {
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let Spellings = ["__builtin_hlsl_dot4add_i8packed"];
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let Attributes = [NoThrow, Const];
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let Prototype = "int(unsigned int, unsigned int, int)";
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}
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def HLSLFrac : LangBuiltin<"HLSL_LANG"> {
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let Spellings = ["__builtin_hlsl_elementwise_frac"];
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let Attributes = [NoThrow, Const];

‎clang/lib/CodeGen/CGBuiltin.cpp

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@@ -18855,7 +18855,17 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned BuiltinID,
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/*ReturnType=*/T0->getScalarType(),
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getDotProductIntrinsic(CGM.getHLSLRuntime(), VecTy0->getElementType()),
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ArrayRef<Value *>{Op0, Op1}, nullptr, "hlsl.dot");
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} break;
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}
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case Builtin::BI__builtin_hlsl_dot4add_i8packed: {
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Value *A = EmitScalarExpr(E->getArg(0));
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Value *B = EmitScalarExpr(E->getArg(1));
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Value *C = EmitScalarExpr(E->getArg(2));
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Intrinsic::ID ID = CGM.getHLSLRuntime().getDot4AddI8PackedIntrinsic();
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return Builder.CreateIntrinsic(
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/*ReturnType=*/C->getType(), ID, ArrayRef<Value *>{A, B, C}, nullptr,
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"hlsl.dot4add.i8packed");
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}
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case Builtin::BI__builtin_hlsl_lerp: {
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Value *X = EmitScalarExpr(E->getArg(0));
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Value *Y = EmitScalarExpr(E->getArg(1));

‎clang/lib/CodeGen/CGHLSLRuntime.h

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@@ -89,6 +89,7 @@ class CGHLSLRuntime {
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GENERATE_HLSL_INTRINSIC_FUNCTION(FDot, fdot)
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GENERATE_HLSL_INTRINSIC_FUNCTION(SDot, sdot)
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GENERATE_HLSL_INTRINSIC_FUNCTION(UDot, udot)
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GENERATE_HLSL_INTRINSIC_FUNCTION(Dot4AddI8Packed, dot4add_i8packed)
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GENERATE_HLSL_INTRINSIC_FUNCTION(WaveIsFirstLane, wave_is_first_lane)
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GENERATE_HLSL_INTRINSIC_FUNCTION(WaveReadLaneAt, wave_readlane)
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‎clang/lib/Headers/hlsl/hlsl_intrinsics.h

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@@ -934,6 +934,16 @@ uint64_t dot(uint64_t3, uint64_t3);
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_HLSL_BUILTIN_ALIAS(__builtin_hlsl_dot)
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uint64_t dot(uint64_t4, uint64_t4);
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//===----------------------------------------------------------------------===//
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// dot4add builtins
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//===----------------------------------------------------------------------===//
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/// \fn int dot4add_i8packed(uint A, uint B, int C)
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_HLSL_AVAILABILITY(shadermodel, 6.4)
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_HLSL_BUILTIN_ALIAS(__builtin_hlsl_dot4add_i8packed)
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int dot4add_i8packed(unsigned int, unsigned int, int);
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//===----------------------------------------------------------------------===//
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// exp builtins
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//===----------------------------------------------------------------------===//

‎clang/test/CodeGenHLSL/builtins/dot4add_i8packed.hlsl

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@@ -0,0 +1,17 @@
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// RUN: %clang_cc1 -finclude-default-header -triple \
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// RUN: dxil-pc-shadermodel6.3-compute %s -emit-llvm -disable-llvm-passes -o - | \
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// RUN: FileCheck %s -DTARGET=dx
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// RUN: %clang_cc1 -finclude-default-header -triple \
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// RUN: spirv-pc-vulkan-compute %s -emit-llvm -disable-llvm-passes -o - | \
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// RUN: FileCheck %s -DTARGET=spv
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// Test basic lowering to runtime function call.
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// CHECK-LABEL: test
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int test(uint a, uint b, int c) {
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// CHECK: %[[RET:.*]] = call [[TY:i32]] @llvm.[[TARGET]].dot4add.i8packed([[TY]] %[[#]], [[TY]] %[[#]], [[TY]] %[[#]])
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// CHECK: ret [[TY]] %[[RET]]
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return dot4add_i8packed(a, b, c);
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}
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// CHECK: declare [[TY]] @llvm.[[TARGET]].dot4add.i8packed([[TY]], [[TY]], [[TY]])

‎clang/test/SemaHLSL/BuiltIns/dot4add_i8packed-errors.hlsl

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@@ -0,0 +1,28 @@
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// RUN: %clang_cc1 -finclude-default-header -triple dxil-pc-shadermodel6.6-library %s -emit-llvm-only -disable-llvm-passes -verify
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int test_too_few_arg0() {
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return __builtin_hlsl_dot4add_i8packed();
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// expected-error@-1 {{too few arguments to function call, expected 3, have 0}}
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}
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int test_too_few_arg1(int p0) {
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return __builtin_hlsl_dot4add_i8packed(p0);
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// expected-error@-1 {{too few arguments to function call, expected 3, have 1}}
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}
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int test_too_few_arg2(int p0) {
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return __builtin_hlsl_dot4add_i8packed(p0, p0);
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// expected-error@-1 {{too few arguments to function call, expected 3, have 2}}
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}
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int test_too_many_arg(int p0) {
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return __builtin_hlsl_dot4add_i8packed(p0, p0, p0, p0);
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// expected-error@-1 {{too many arguments to function call, expected 3, have 4}}
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}
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struct S { float f; };
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int test_expr_struct_type_check(S p0, int p1) {
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return __builtin_hlsl_dot4add_i8packed(p0, p1, p1);
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// expected-error@-1 {{no viable conversion from 'S' to 'unsigned int'}}
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}

‎llvm/docs/SPIRVUsage.rst

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@@ -179,6 +179,8 @@ list of supported SPIR-V extensions, sorted alphabetically by their extension na
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- Provides additional information to a compiler, similar to the llvm.assume and llvm.expect intrinsics.
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* - ``SPV_KHR_float_controls``
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- Provides new execution modes to control floating-point computations by overriding an implementation’s default behavior for rounding modes, denormals, signed zero, and infinities.
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* - ``SPV_KHR_integer_dot_product``
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- Adds instructions for dot product operations on integer vectors with optional accumulation. Integer vectors includes 4-component vector of 8 bit integers and 4-component vectors of 8 bit integers packed into 32-bit integers.
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* - ``SPV_KHR_linkonce_odr``
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- Allows to use the LinkOnceODR linkage type that lets a function or global variable to be merged with other functions or global variables of the same name when linkage occurs.
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* - ``SPV_KHR_no_integer_wrap_decoration``

‎llvm/include/llvm/IR/IntrinsicsDirectX.td

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@@ -69,6 +69,7 @@ def int_dx_udot :
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DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
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[llvm_anyint_ty, LLVMScalarOrSameVectorWidth<0, LLVMVectorElementType<0>>],
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[IntrNoMem, Commutative] >;
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def int_dx_dot4add_i8packed : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_dx_frac : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
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def int_dx_degrees : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty], [IntrNoMem]>;

‎llvm/include/llvm/IR/IntrinsicsSPIRV.td

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@@ -83,6 +83,7 @@ let TargetPrefix = "spv" in {
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DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
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[llvm_anyint_ty, LLVMScalarOrSameVectorWidth<0, LLVMVectorElementType<0>>],
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[IntrNoMem, Commutative] >;
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def int_spv_dot4add_i8packed : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_spv_wave_is_first_lane : DefaultAttrsIntrinsic<[llvm_i1_ty], [], [IntrConvergent]>;
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def int_spv_wave_readlane : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>, llvm_i32_ty], [IntrConvergent, IntrNoMem]>;
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def int_spv_sign : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>], [llvm_any_ty], [IntrNoMem]>;

‎llvm/lib/Target/DirectX/DXIL.td

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@@ -788,6 +788,16 @@ def SplitDouble : DXILOp<102, splitDouble> {
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let attributes = [Attributes<DXIL1_0, [ReadNone]>];
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}
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def Dot4AddI8Packed : DXILOp<163, dot4AddPacked> {
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let Doc = "signed dot product of 4 x i8 vectors packed into i32, with "
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"accumulate to i32";
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let LLVMIntrinsic = int_dx_dot4add_i8packed;
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let arguments = [Int32Ty, Int32Ty, Int32Ty];
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let result = Int32Ty;
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let attributes = [Attributes<DXIL1_0, [ReadNone]>];
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let stages = [Stages<DXIL1_0, [all_stages]>];
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}
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def AnnotateHandle : DXILOp<216, annotateHandle> {
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let Doc = "annotate handle with resource properties";
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let arguments = [HandleTy, ResPropsTy];

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