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[𝘀𝗽𝗿] initial version
Created using spr 1.3.6-beta.1
2 parents e57f4e8 + fb286cb commit 3cde466

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-67
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5 files changed

+41
-67
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‎llvm/include/llvm/TargetParser/RISCVTargetParser.h‎

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -24,14 +24,6 @@ class Triple;
2424

2525
namespace RISCV {
2626

27-
namespace RISCVExtensionBitmaskTable {
28-
struct RISCVExtensionBitmask {
29-
const char *Name;
30-
unsigned GroupID;
31-
unsigned BitPosition;
32-
};
33-
} // namespace RISCVExtensionBitmaskTable
34-
3527
struct CPUModel {
3628
uint32_t MVendorID;
3729
uint64_t MArchID;

‎llvm/lib/Target/RISCV/RISCVFeatures.td‎

Lines changed: 24 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -154,7 +154,8 @@ def FeatureStdExtZihpm
154154
: RISCVExtension<2, 0, "Hardware Performance Counters",
155155
[FeatureStdExtZicsr]>;
156156

157-
def FeatureStdExtZimop : RISCVExtension<1, 0, "May-Be-Operations">;
157+
def FeatureStdExtZimop : RISCVExtension<1, 0, "May-Be-Operations">,
158+
RISCVExtensionBitmask<1, 1>;
158159
def HasStdExtZimop : Predicate<"Subtarget->hasStdExtZimop()">,
159160
AssemblerPredicate<(all_of FeatureStdExtZimop),
160161
"'Zimop' (May-Be-Operations)">;
@@ -262,7 +263,8 @@ def HasStdExtZalasr : Predicate<"Subtarget->hasStdExtZalasr()">,
262263
def FeatureStdExtZama16b
263264
: RISCVExtension<1, 0, "Atomic 16-byte misaligned loads, stores and AMOs">;
264265

265-
def FeatureStdExtZawrs : RISCVExtension<1, 0, "Wait on Reservation Set">;
266+
def FeatureStdExtZawrs : RISCVExtension<1, 0, "Wait on Reservation Set">,
267+
RISCVExtensionBitmask<1, 7>;
266268
def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
267269
AssemblerPredicate<(all_of FeatureStdExtZawrs),
268270
"'Zawrs' (Wait on Reservation Set)">;
@@ -368,7 +370,8 @@ def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
368370
def FeatureStdExtZca
369371
: RISCVExtension<1, 0,
370372
"part of the C extension, excluding compressed "
371-
"floating point loads/stores">;
373+
"floating point loads/stores">,
374+
RISCVExtensionBitmask<1, 2>;
372375

373376
def FeatureStdExtC
374377
: RISCVExtension<2, 0, "Compressed Instructions", [FeatureStdExtZca]>,
@@ -387,15 +390,17 @@ def HasStdExtCOrZca
387390

388391
def FeatureStdExtZcb
389392
: RISCVExtension<1, 0, "Compressed basic bit manipulation instructions",
390-
[FeatureStdExtZca]>;
393+
[FeatureStdExtZca]>,
394+
RISCVExtensionBitmask<1, 3>;
391395
def HasStdExtZcb : Predicate<"Subtarget->hasStdExtZcb()">,
392396
AssemblerPredicate<(all_of FeatureStdExtZcb),
393397
"'Zcb' (Compressed basic bit manipulation instructions)">;
394398

395399
def FeatureStdExtZcd
396400
: RISCVExtension<1, 0,
397401
"Compressed Double-Precision Floating-Point Instructions",
398-
[FeatureStdExtD, FeatureStdExtZca]>;
402+
[FeatureStdExtD, FeatureStdExtZca]>,
403+
RISCVExtensionBitmask<1, 4>;
399404

400405
def HasStdExtCOrZcd
401406
: Predicate<"Subtarget->hasStdExtCOrZcd()">,
@@ -406,7 +411,8 @@ def HasStdExtCOrZcd
406411
def FeatureStdExtZcf
407412
: RISCVExtension<1, 0,
408413
"Compressed Single-Precision Floating-Point Instructions",
409-
[FeatureStdExtF, FeatureStdExtZca]>;
414+
[FeatureStdExtF, FeatureStdExtZca]>,
415+
RISCVExtensionBitmask<1, 5>;
410416

411417
def FeatureStdExtZclsd
412418
: RISCVExtension<1, 0,
@@ -447,7 +453,8 @@ def HasStdExtCOrZcfOrZce
447453

448454
def FeatureStdExtZcmop
449455
: RISCVExtension<1, 0, "Compressed May-Be-Operations",
450-
[FeatureStdExtZca]>;
456+
[FeatureStdExtZca]>,
457+
RISCVExtensionBitmask<1, 6>;
451458
def HasStdExtZcmop : Predicate<"Subtarget->hasStdExtZcmop()">,
452459
AssemblerPredicate<(all_of FeatureStdExtZcmop),
453460
"'Zcmop' (Compressed May-Be-Operations)">;
@@ -628,32 +635,37 @@ def FeatureStdExtZve32x
628635
: RISCVExtension<1, 0,
629636
"Vector Extensions for Embedded Processors "
630637
"with maximal 32 EEW",
631-
[FeatureStdExtZicsr, FeatureStdExtZvl32b]>;
638+
[FeatureStdExtZicsr, FeatureStdExtZvl32b]>,
639+
RISCVExtensionBitmask<0, 60>;
632640

633641

634642
def FeatureStdExtZve32f
635643
: RISCVExtension<1, 0,
636644
"Vector Extensions for Embedded Processors "
637645
"with maximal 32 EEW and F extension",
638-
[FeatureStdExtZve32x, FeatureStdExtF]>;
646+
[FeatureStdExtZve32x, FeatureStdExtF]>,
647+
RISCVExtensionBitmask<0, 61>;
639648

640649
def FeatureStdExtZve64x
641650
: RISCVExtension<1, 0,
642651
"Vector Extensions for Embedded Processors "
643652
"with maximal 64 EEW",
644-
[FeatureStdExtZve32x, FeatureStdExtZvl64b]>;
653+
[FeatureStdExtZve32x, FeatureStdExtZvl64b]>,
654+
RISCVExtensionBitmask<0, 62>;
645655

646656
def FeatureStdExtZve64f
647657
: RISCVExtension<1, 0,
648658
"Vector Extensions for Embedded Processors "
649659
"with maximal 64 EEW and F extension",
650-
[FeatureStdExtZve32f, FeatureStdExtZve64x]>;
660+
[FeatureStdExtZve32f, FeatureStdExtZve64x]>,
661+
RISCVExtensionBitmask<0, 63>;
651662

652663
def FeatureStdExtZve64d
653664
: RISCVExtension<1, 0,
654665
"Vector Extensions for Embedded Processors "
655666
"with maximal 64 EEW, F and D extension",
656-
[FeatureStdExtZve64f, FeatureStdExtD]>;
667+
[FeatureStdExtZve64f, FeatureStdExtD]>,
668+
RISCVExtensionBitmask<1, 0>;
657669

658670
def FeatureStdExtV
659671
: RISCVExtension<1, 0,

‎llvm/lib/TargetParser/RISCVISAInfo.cpp‎

Lines changed: 11 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -1048,41 +1048,21 @@ struct RISCVExtBit {
10481048
uint8_t bitpos;
10491049
};
10501050

1051-
constexpr static RISCVExtBit RISCVBitPositions[] = {
1052-
{"a", 0, 0}, {"c", 0, 2},
1053-
{"d", 0, 3}, {"f", 0, 5},
1054-
{"i", 0, 8}, {"m", 0, 12},
1055-
{"v", 0, 21}, {"zacas", 0, 26},
1056-
{"zba", 0, 27}, {"zbb", 0, 28},
1057-
{"zbc", 0, 29}, {"zbkb", 0, 30},
1058-
{"zbkc", 0, 31}, {"zbkx", 0, 32},
1059-
{"zbs", 0, 33}, {"zfa", 0, 34},
1060-
{"zfh", 0, 35}, {"zfhmin", 0, 36},
1061-
{"zicboz", 0, 37}, {"zicond", 0, 38},
1062-
{"zihintntl", 0, 39}, {"zihintpause", 0, 40},
1063-
{"zknd", 0, 41}, {"zkne", 0, 42},
1064-
{"zknh", 0, 43}, {"zksed", 0, 44},
1065-
{"zksh", 0, 45}, {"zkt", 0, 46},
1066-
{"ztso", 0, 47}, {"zvbb", 0, 48},
1067-
{"zvbc", 0, 49}, {"zvfh", 0, 50},
1068-
{"zvfhmin", 0, 51}, {"zvkb", 0, 52},
1069-
{"zvkg", 0, 53}, {"zvkned", 0, 54},
1070-
{"zvknha", 0, 55}, {"zvknhb", 0, 56},
1071-
{"zvksed", 0, 57}, {"zvksh", 0, 58},
1072-
{"zvkt", 0, 59}, {"zve32x", 0, 60},
1073-
{"zve32f", 0, 61}, {"zve64x", 0, 62},
1074-
{"zve64f", 0, 63}, {"zve64d", 1, 0},
1075-
{"zimop", 1, 1}, {"zca", 1, 2},
1076-
{"zcb", 1, 3}, {"zcd", 1, 4},
1077-
{"zcf", 1, 5}, {"zcmop", 1, 6},
1078-
{"zawrs", 1, 7}};
1051+
struct RISCVExtensionBitmask {
1052+
const char *Name;
1053+
unsigned GroupID;
1054+
unsigned BitPosition;
1055+
};
1056+
1057+
#define GET_RISCVExtensionBitmaskTable_IMPL
1058+
#include "llvm/TargetParser/RISCVTargetParserDef.inc"
10791059

10801060
std::pair<int, int> RISCVISAInfo::getRISCVFeaturesBitsInfo(StringRef Ext) {
10811061
// Note that this code currently accepts mixed case extension names, but
10821062
// does not handle extension versions at all. That's probably fine because
10831063
// there's only one extension version in the __riscv_feature_bits vector.
1084-
for (auto E : RISCVBitPositions)
1085-
if (E.ext.equals_insensitive(Ext))
1086-
return std::make_pair(E.groupid, E.bitpos);
1064+
for (auto E : ExtensionBitmask)
1065+
if (Ext.equals_insensitive(E.Name))
1066+
return std::make_pair(E.GroupID, E.BitPosition);
10871067
return std::make_pair(-1, -1);
10881068
}

‎llvm/lib/TargetParser/RISCVTargetParser.cpp‎

Lines changed: 0 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -138,21 +138,6 @@ void getFeaturesForCPU(StringRef CPU,
138138
EnabledFeatures.push_back(F.substr(1));
139139
}
140140

141-
namespace RISCVExtensionBitmaskTable {
142-
#define GET_RISCVExtensionBitmaskTable_IMPL
143-
#include "llvm/TargetParser/RISCVTargetParserDef.inc"
144-
145-
} // namespace RISCVExtensionBitmaskTable
146-
147-
namespace {
148-
struct LessExtName {
149-
bool operator()(const RISCVExtensionBitmaskTable::RISCVExtensionBitmask &LHS,
150-
StringRef RHS) {
151-
return StringRef(LHS.Name) < RHS;
152-
}
153-
};
154-
} // namespace
155-
156141
} // namespace RISCV
157142

158143
namespace RISCVVType {

‎llvm/utils/TableGen/Basic/RISCVTargetDefEmitter.cpp‎

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -224,7 +224,12 @@ static void emitRISCVExtensionBitmask(const RecordKeeper &RK, raw_ostream &OS) {
224224
std::vector<const Record *> Extensions =
225225
RK.getAllDerivedDefinitionsIfDefined("RISCVExtensionBitmask");
226226
llvm::sort(Extensions, [](const Record *Rec1, const Record *Rec2) {
227-
return getExtensionName(Rec1) < getExtensionName(Rec2);
227+
unsigned GroupID1 = Rec1->getValueAsInt("GroupID");
228+
unsigned GroupID2 = Rec2->getValueAsInt("GroupID");
229+
if (GroupID1 != GroupID2)
230+
return GroupID1 < GroupID2;
231+
232+
return Rec1->getValueAsInt("BitPos") < Rec2->getValueAsInt("BitPos");
228233
});
229234

230235
#ifndef NDEBUG

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