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1 parent fbb0f2d commit 3ce0ea3Copy full SHA for 3ce0ea3
llvm/lib/Target/AMDGPU/SIDefines.h
@@ -572,7 +572,17 @@ enum ModeRegisterMasks : uint32_t {
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GPR_IDX_EN_MASK = 1 << 27,
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VSKIP_MASK = 1 << 28,
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- CSP_MASK = 0x7u << 29 // Bits 29..31
+ CSP_MASK = 0x7u << 29, // Bits 29..31
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+
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+ // GFX1250
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+ DST_VGPR_MSB = 1 << 12,
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+ SRC0_VGPR_MSB = 1 << 13,
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+ SRC1_VGPR_MSB = 1 << 14,
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+ SRC2_VGPR_MSB = 1 << 15,
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+ VGPR_MSB_MASK = 0xf << 12, // Bits 12..15
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+ REPLAY_MODE = 1 << 25,
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+ FLAT_SCRATCH_IS_NV = 1 << 26,
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};
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} // namespace Hwreg
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