!fixup address comments, thanks

Author: fhahn

llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp

@@ -3288,10 +3288,10 @@ void VPlanTransforms::materializeVectorTripCount(VPlan &Plan,
   // IR value has already been set.
   if (VectorTC.getNumUsers() == 0 || VectorTC.getLiveInIRValue())
     return;
+
   VPValue *TC = Plan.getTripCount();
   Type *TCTy = VPTypeAnalysis(Plan).inferScalarType(TC);
   VPBuilder Builder(VectorPHVPBB, VectorPHVPBB->begin());
-
   VPValue *Step = &Plan.getVFxUF();
 
   // If the tail is to be folded by masking, round the number of iterations N
@@ -3327,14 +3327,14 @@ void VPlanTransforms::materializeVectorTripCount(VPlan &Plan,
   // since there will already be scalar iterations. Note that the minimum
   // iterations check ensures that N >= Step.
   if (RequiresScalarEpilogue) {
-    auto *IsZero = Builder.createICmp(
+    VPValue *IsZero = Builder.createICmp(
         CmpInst::ICMP_EQ, R, Plan.getOrAddLiveIn(ConstantInt::get(TCTy, 0)));
     R = Builder.createSelect(IsZero, Step, R);
   }
 
-  auto Res = Builder.createNaryOp(Instruction::Sub, {TC, R},
-                                  DebugLoc::getCompilerGenerated(), "n.vec");
-  Plan.getVectorTripCount().replaceAllUsesWith(Res);
+  VPValue *Res = Builder.createNaryOp(
+      Instruction::Sub, {TC, R}, DebugLoc::getCompilerGenerated(), "n.vec");
+  VectorTC.replaceAllUsesWith(Res);
 }
 
 /// Returns true if \p V is VPWidenLoadRecipe or VPInterleaveRecipe that can be

llvm/test/Transforms/LoopVectorize/AArch64/sve-low-trip-count.ll

@@ -9,12 +9,6 @@ define void @trip7_i64(ptr noalias nocapture noundef %dst, ptr noalias nocapture
 ; CHECK-NEXT:  [[ENTRY:.*:]]
 ; CHECK-NEXT:    br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
 ; CHECK:       [[VECTOR_PH]]:
-; CHECK-NEXT:    [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
-; CHECK-NEXT:    [[TMP1:%.*]] = mul nuw i64 [[TMP0]], 2
-; CHECK-NEXT:    [[TMP2:%.*]] = sub i64 [[TMP1]], 1
-; CHECK-NEXT:    [[N_RND_UP:%.*]] = add i64 7, [[TMP2]]
-; CHECK-NEXT:    [[N_MOD_VF:%.*]] = urem i64 [[N_RND_UP]], [[TMP1]]
-; CHECK-NEXT:    [[N_VEC:%.*]] = sub i64 [[N_RND_UP]], [[N_MOD_VF]]
 ; CHECK-NEXT:    [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
 ; CHECK-NEXT:    [[TMP4:%.*]] = mul nuw i64 [[TMP3]], 2
 ; CHECK-NEXT:    [[ACTIVE_LANE_MASK_ENTRY:%.*]] = call <vscale x 2 x i1> @llvm.get.active.lane.mask.nxv2i1.i64(i64 0, i64 7)