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!fixup rebase on top of latest main
1 parent 3636767 commit 3d0fde8

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+79
-142
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2 files changed

+79
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‎llvm/lib/CodeGen/SelectOptimize.cpp‎

Lines changed: 21 additions & 102 deletions
Original file line numberDiff line numberDiff line change
@@ -138,49 +138,8 @@ class SelectOptimizeImpl {
138138
unsigned CondIdx;
139139

140140
public:
141-
<<<<<<< HEAD
142141
SelectLike(Instruction *I, bool Inverted = false, unsigned CondIdx = 0)
143142
: I(I), Inverted(Inverted), CondIdx(CondIdx) {}
144-
=======
145-
/// Match a select or select-like instruction, returning a SelectLike.
146-
static SelectLike match(Instruction *I) {
147-
// Select instruction are what we are usually looking for.
148-
if (isa<SelectInst>(I))
149-
return SelectLike(I);
150-
151-
// An Or(zext(i1 X), Y) can also be treated like a select, with condition
152-
// C and values Y|1 and Y.
153-
switch (I->getOpcode()) {
154-
case Instruction::Add:
155-
case Instruction::Or:
156-
case Instruction::Sub: {
157-
Value *X;
158-
if ((PatternMatch::match(I->getOperand(0),
159-
m_OneUse(m_ZExt(m_Value(X)))) ||
160-
PatternMatch::match(I->getOperand(1),
161-
m_OneUse(m_ZExt(m_Value(X))))) &&
162-
X->getType()->isIntegerTy(1))
163-
return SelectLike(I);
164-
break;
165-
}
166-
}
167-
168-
return SelectLike(nullptr);
169-
}
170-
171-
bool isValid() { return I; }
172-
operator bool() { return isValid(); }
173-
174-
/// Invert the select by inverting the condition and switching the operands.
175-
void setInverted() {
176-
assert(!Inverted && "Trying to invert an inverted SelectLike");
177-
assert(isa<Instruction>(getCondition()) &&
178-
cast<Instruction>(getCondition())->getOpcode() ==
179-
Instruction::Xor);
180-
Inverted = true;
181-
}
182-
bool isInverted() const { return Inverted; }
183-
>>>>>>> 7e5ca4eafa3c ([SelectOpt] Support add and sub with zext operands.)
184143

185144
Instruction *getI() { return I; }
186145
const Instruction *getI() const { return I; }
@@ -236,7 +195,6 @@ class SelectOptimizeImpl {
236195
return It != InstCostMap.end() ? It->second.NonPredCost
237196
: Scaled64::getZero();
238197
}
239-
<<<<<<< HEAD
240198
return Scaled64::getZero();
241199
}
242200
// If getTrue(False)Value() return nullptr, it means we are dealing with
@@ -254,48 +212,6 @@ class SelectOptimizeImpl {
254212
TotalCost += It->second.NonPredCost;
255213
}
256214
return TotalCost;
257-
=======
258-
259-
// BinaryOp case - add the cost of an extra BinOp to the cost of the False
260-
// case.
261-
if (isa<BinaryOperator>(I)) {
262-
if (auto OpI = dyn_cast<Instruction>(getFalseValue())) {
263-
auto It = InstCostMap.find(I);
264-
if (It != InstCostMap.end()) {
265-
InstructionCost OrCost = TTI->getArithmeticInstrCost(
266-
I->getOpcode(), OpI->getType(),
267-
TargetTransformInfo::TCK_Latency,
268-
{TargetTransformInfo::OK_AnyValue,
269-
TargetTransformInfo::OP_None},
270-
{TTI::OK_UniformConstantValue, TTI::OP_PowerOf2});
271-
return It->second.NonPredCost + Scaled64::get(*OrCost.getValue());
272-
}
273-
}
274-
}
275-
276-
return Scaled64::getZero();
277-
}
278-
279-
/// Return the NonPredCost cost of the false op, given the costs in
280-
/// InstCostMap. This may need to be generated for select-like instructions.
281-
Scaled64
282-
getFalseOpCost(DenseMap<const Instruction *, CostInfo> &InstCostMap,
283-
const TargetTransformInfo *TTI) {
284-
if (isa<SelectInst>(I))
285-
if (auto *I = dyn_cast<Instruction>(getFalseValue())) {
286-
auto It = InstCostMap.find(I);
287-
return It != InstCostMap.end() ? It->second.NonPredCost
288-
: Scaled64::getZero();
289-
}
290-
291-
// Or case - return the cost of the false case
292-
if (isa<BinaryOperator>(I))
293-
if (auto I = dyn_cast<Instruction>(getFalseValue()))
294-
if (auto It = InstCostMap.find(I); It != InstCostMap.end())
295-
return It->second.NonPredCost;
296-
297-
return Scaled64::getZero();
298-
>>>>>>> 7e5ca4eafa3c ([SelectOpt] Support add and sub with zext operands.)
299215
}
300216
};
301217

@@ -572,23 +488,11 @@ static Value *getTrueOrFalseValue(
572488
return V;
573489
}
574490

575-
<<<<<<< HEAD
576491
auto *BO = cast<BinaryOperator>(SI.getI());
577-
assert(BO->getOpcode() == Instruction::Or &&
578-
"Only currently handling Or instructions.");
579-
=======
580-
if (auto *BinOp = dyn_cast<BinaryOperator>(SI.getI())) {
581-
assert((BinOp->getOpcode() == Instruction::Add ||
582-
BinOp->getOpcode() == Instruction::Or ||
583-
BinOp->getOpcode() == Instruction::Sub) &&
584-
"Only currently handling Add, Or and Sub instructions.");
585-
V = SI.getFalseValue();
586-
if (isTrue) {
587-
Constant *CI = ConstantInt::get(V->getType(), 1);
588-
V = IB.CreateBinOp(BinOp->getOpcode(), V, CI);
589-
}
590-
}
591-
>>>>>>> 7e5ca4eafa3c ([SelectOpt] Support add and sub with zext operands.)
492+
assert((BO->getOpcode() == Instruction::Add ||
493+
BO->getOpcode() == Instruction::Or ||
494+
BO->getOpcode() == Instruction::Sub) &&
495+
"Only currently handling Add, Or and Sub binary operators.");
592496

593497
auto *CBO = BO->clone();
594498
auto CondIdx = SI.getConditionOpIndex();
@@ -884,8 +788,23 @@ void SelectOptimizeImpl::collectSelectGroups(BasicBlock &BB,
884788
// An Or(zext(i1 X), Y) can also be treated like a select, with condition X
885789
// and values Y|1 and Y.
886790
if (auto *BO = dyn_cast<BinaryOperator>(I)) {
887-
if (BO->getType()->isIntegerTy(1) || BO->getOpcode() != Instruction::Or)
888-
return SelectInfo.end();
791+
switch (I->getOpcode()) {
792+
case Instruction::Add:
793+
case Instruction::Sub: {
794+
Value *X;
795+
if (!((PatternMatch::match(I->getOperand(0),
796+
m_OneUse(m_ZExt(m_Value(X)))) ||
797+
PatternMatch::match(I->getOperand(1),
798+
m_OneUse(m_ZExt(m_Value(X))))) &&
799+
X->getType()->isIntegerTy(1)))
800+
return SelectInfo.end();
801+
break;
802+
}
803+
case Instruction::Or:
804+
if (BO->getType()->isIntegerTy(1) || BO->getOpcode() != Instruction::Or)
805+
return SelectInfo.end();
806+
break;
807+
}
889808

890809
for (unsigned Idx = 0; Idx < 2; Idx++) {
891810
auto *Op = BO->getOperand(Idx);

‎llvm/test/CodeGen/AArch64/selectopt-cast.ll‎

Lines changed: 58 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -17,12 +17,12 @@ define void @test_add_zext(ptr %dst, ptr %src, i64 %j.start, i64 %p, i64 %i.star
1717
; CHECK-NEXT: [[CMP3:%.*]] = icmp ult ptr [[L_I]], [[L_J]]
1818
; CHECK-NEXT: [[DEC:%.*]] = zext i1 [[CMP3]] to i64
1919
; CHECK-NEXT: [[CMP3_FROZEN:%.*]] = freeze i1 [[CMP3]]
20-
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[J]], 1
21-
; CHECK-NEXT: br i1 [[CMP3_FROZEN]], label [[SELECT_END]], label [[SELECT_FALSE:%.*]]
22-
; CHECK: select.false:
20+
; CHECK-NEXT: br i1 [[CMP3_FROZEN]], label [[SELECT_TRUE_SINK:%.*]], label [[SELECT_END]]
21+
; CHECK: select.true.sink:
22+
; CHECK-NEXT: [[TMP0:%.*]] = add nsw i64 [[J]], 1
2323
; CHECK-NEXT: br label [[SELECT_END]]
2424
; CHECK: select.end:
25-
; CHECK-NEXT: [[J_NEXT]] = phi i64 [ [[TMP0]], [[LOOP]] ], [ [[J]], [[SELECT_FALSE]] ]
25+
; CHECK-NEXT: [[J_NEXT]] = phi i64 [ [[TMP0]], [[SELECT_TRUE_SINK]] ], [ [[J]], [[LOOP]] ]
2626
; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds ptr, ptr [[DST:%.*]], i64 [[IV]]
2727
; CHECK-NEXT: store i64 [[J_NEXT]], ptr [[GEP_DST]], align 8
2828
; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
@@ -60,20 +60,26 @@ define void @test_add_zext_first_op(ptr %dst, ptr %src, i64 %j.start, i64 %p, i6
6060
; CHECK-NEXT: entry:
6161
; CHECK-NEXT: br label [[LOOP:%.*]]
6262
; CHECK: loop:
63-
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
64-
; CHECK-NEXT: [[J:%.*]] = phi i64 [ [[J_START:%.*]], [[ENTRY]] ], [ [[J_NEXT:%.*]], [[LOOP]] ]
65-
; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[I_START:%.*]], [[ENTRY]] ], [ [[J_NEXT]], [[LOOP]] ]
66-
; CHECK-NEXT: [[GEP_I:%.*]] = getelementptr inbounds ptr, ptr [[SRC:%.*]], i64 [[I]]
67-
; CHECK-NEXT: [[L_I:%.*]] = load ptr, ptr [[GEP_I]], align 8
68-
; CHECK-NEXT: [[GEP_J:%.*]] = getelementptr inbounds ptr, ptr [[SRC]], i64 [[J]]
63+
; CHECK-NEXT: [[IV1:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[SELECT_END:%.*]] ]
64+
; CHECK-NEXT: [[J:%.*]] = phi i64 [ [[J_START:%.*]], [[ENTRY]] ], [ [[J_NEXT:%.*]], [[SELECT_END]] ]
65+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[I_START:%.*]], [[ENTRY]] ], [ [[J_NEXT]], [[SELECT_END]] ]
66+
; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds ptr, ptr [[DST:%.*]], i64 [[IV]]
67+
; CHECK-NEXT: [[L_I:%.*]] = load ptr, ptr [[GEP_DST]], align 8
68+
; CHECK-NEXT: [[GEP_J:%.*]] = getelementptr inbounds ptr, ptr [[DST]], i64 [[J]]
6969
; CHECK-NEXT: [[L_J:%.*]] = load ptr, ptr [[GEP_J]], align 8
7070
; CHECK-NEXT: [[CMP3:%.*]] = icmp ult ptr [[L_I]], [[L_J]]
7171
; CHECK-NEXT: [[DEC:%.*]] = zext i1 [[CMP3]] to i64
72-
; CHECK-NEXT: [[J_NEXT]] = add nsw i64 [[DEC]], [[J]]
73-
; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds ptr, ptr [[DST:%.*]], i64 [[IV]]
74-
; CHECK-NEXT: store i64 [[J_NEXT]], ptr [[GEP_DST]], align 8
75-
; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
76-
; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], [[J_START]]
72+
; CHECK-NEXT: [[CMP3_FROZEN:%.*]] = freeze i1 [[CMP3]]
73+
; CHECK-NEXT: br i1 [[CMP3_FROZEN]], label [[SELECT_TRUE_SINK:%.*]], label [[SELECT_END]]
74+
; CHECK: select.true.sink:
75+
; CHECK-NEXT: [[TMP0:%.*]] = add nsw i64 1, [[J]]
76+
; CHECK-NEXT: br label [[SELECT_END]]
77+
; CHECK: select.end:
78+
; CHECK-NEXT: [[J_NEXT]] = phi i64 [ [[TMP0]], [[SELECT_TRUE_SINK]] ], [ [[J]], [[LOOP]] ]
79+
; CHECK-NEXT: [[GEP_DST1:%.*]] = getelementptr inbounds ptr, ptr [[DST1:%.*]], i64 [[IV1]]
80+
; CHECK-NEXT: store i64 [[J_NEXT]], ptr [[GEP_DST1]], align 8
81+
; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV1]], 1
82+
; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV1]], [[J_START]]
7783
; CHECK-NEXT: br i1 [[EC]], label [[EXIT:%.*]], label [[LOOP]]
7884
; CHECK: exit:
7985
; CHECK-NEXT: ret void
@@ -107,20 +113,23 @@ define void @test_add_zext_not(ptr %dst, ptr %src, i64 %j.start, i64 %p, i64 %i.
107113
; CHECK-NEXT: entry:
108114
; CHECK-NEXT: br label [[LOOP:%.*]]
109115
; CHECK: loop:
116+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[SELECT_END:%.*]] ]
117+
; CHECK-NEXT: [[J:%.*]] = phi i64 [ [[J_START:%.*]], [[ENTRY]] ], [ [[J_NEXT:%.*]], [[SELECT_END]] ]
118+
; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[I_START:%.*]], [[ENTRY]] ], [ [[J_NEXT]], [[SELECT_END]] ]
110119
; CHECK-NEXT: [[GEP_I:%.*]] = getelementptr inbounds ptr, ptr [[SRC:%.*]], i64 [[I]]
111120
; CHECK-NEXT: [[L_I:%.*]] = load ptr, ptr [[GEP_I]], align 8
112121
; CHECK-NEXT: [[GEP_J:%.*]] = getelementptr inbounds ptr, ptr [[SRC]], i64 [[J]]
113122
; CHECK-NEXT: [[L_J:%.*]] = load ptr, ptr [[GEP_J]], align 8
114123
; CHECK-NEXT: [[CMP3:%.*]] = icmp ult ptr [[L_I]], [[L_J]]
115124
; CHECK-NEXT: [[NOT_CMP3:%.*]] = xor i1 [[CMP3]], true
116125
; CHECK-NEXT: [[DEC:%.*]] = zext i1 [[NOT_CMP3]] to i64
117-
; CHECK-NEXT: [[NOT_CMP3_FROZEN:%.*]] = freeze i1 [[NOT_CMP3]]
118-
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[J]], 1
119-
; CHECK-NEXT: br i1 [[NOT_CMP3_FROZEN]], label [[SELECT_END]], label [[SELECT_FALSE:%.*]]
120-
; CHECK: select.false:
126+
; CHECK-NEXT: [[CMP3_FROZEN:%.*]] = freeze i1 [[CMP3]]
127+
; CHECK-NEXT: br i1 [[CMP3_FROZEN]], label [[SELECT_END]], label [[SELECT_FALSE_SINK:%.*]]
128+
; CHECK: select.false.sink:
129+
; CHECK-NEXT: [[TMP0:%.*]] = add nsw i64 [[J]], 1
121130
; CHECK-NEXT: br label [[SELECT_END]]
122131
; CHECK: select.end:
123-
; CHECK-NEXT: [[J_NEXT]] = phi i64 [ [[TMP0]], [[LOOP]] ], [ [[J]], [[SELECT_FALSE]] ]
132+
; CHECK-NEXT: [[J_NEXT]] = phi i64 [ [[J]], [[LOOP]] ], [ [[TMP0]], [[SELECT_FALSE_SINK]] ]
124133
; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds ptr, ptr [[DST:%.*]], i64 [[IV]]
125134
; CHECK-NEXT: store i64 [[J_NEXT]], ptr [[GEP_DST]], align 8
126135
; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
@@ -375,12 +384,12 @@ define void @test_sub_zext(ptr %dst, ptr %src, i64 %j.start, i64 %p, i64 %i.star
375384
; CHECK-NEXT: [[CMP3:%.*]] = icmp ult ptr [[L_I]], [[L_J]]
376385
; CHECK-NEXT: [[DEC:%.*]] = zext i1 [[CMP3]] to i64
377386
; CHECK-NEXT: [[CMP3_FROZEN:%.*]] = freeze i1 [[CMP3]]
378-
; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[J]], 1
379-
; CHECK-NEXT: br i1 [[CMP3_FROZEN]], label [[SELECT_END]], label [[SELECT_FALSE:%.*]]
380-
; CHECK: select.false:
387+
; CHECK-NEXT: br i1 [[CMP3_FROZEN]], label [[SELECT_TRUE_SINK:%.*]], label [[SELECT_END]]
388+
; CHECK: select.true.sink:
389+
; CHECK-NEXT: [[TMP0:%.*]] = sub nsw i64 [[J]], 1
381390
; CHECK-NEXT: br label [[SELECT_END]]
382391
; CHECK: select.end:
383-
; CHECK-NEXT: [[J_NEXT]] = phi i64 [ [[TMP0]], [[LOOP]] ], [ [[J]], [[SELECT_FALSE]] ]
392+
; CHECK-NEXT: [[J_NEXT]] = phi i64 [ [[TMP0]], [[SELECT_TRUE_SINK]] ], [ [[J]], [[LOOP]] ]
384393
; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds ptr, ptr [[DST:%.*]], i64 [[IV]]
385394
; CHECK-NEXT: store i64 [[J_NEXT]], ptr [[GEP_DST]], align 8
386395
; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
@@ -418,20 +427,26 @@ define void @test_sub_zext_first_op(ptr %dst, ptr %src, i64 %j.start, i64 %p, i6
418427
; CHECK-NEXT: entry:
419428
; CHECK-NEXT: br label [[LOOP:%.*]]
420429
; CHECK: loop:
421-
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
422-
; CHECK-NEXT: [[J:%.*]] = phi i64 [ [[J_START:%.*]], [[ENTRY]] ], [ [[J_NEXT:%.*]], [[LOOP]] ]
423-
; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[I_START:%.*]], [[ENTRY]] ], [ [[J_NEXT]], [[LOOP]] ]
424-
; CHECK-NEXT: [[GEP_I:%.*]] = getelementptr inbounds ptr, ptr [[SRC:%.*]], i64 [[I]]
425-
; CHECK-NEXT: [[L_I:%.*]] = load ptr, ptr [[GEP_I]], align 8
426-
; CHECK-NEXT: [[GEP_J:%.*]] = getelementptr inbounds ptr, ptr [[SRC]], i64 [[J]]
430+
; CHECK-NEXT: [[IV1:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[SELECT_END:%.*]] ]
431+
; CHECK-NEXT: [[J:%.*]] = phi i64 [ [[J_START:%.*]], [[ENTRY]] ], [ [[J_NEXT:%.*]], [[SELECT_END]] ]
432+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[I_START:%.*]], [[ENTRY]] ], [ [[J_NEXT]], [[SELECT_END]] ]
433+
; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds ptr, ptr [[DST:%.*]], i64 [[IV]]
434+
; CHECK-NEXT: [[L_I:%.*]] = load ptr, ptr [[GEP_DST]], align 8
435+
; CHECK-NEXT: [[GEP_J:%.*]] = getelementptr inbounds ptr, ptr [[DST]], i64 [[J]]
427436
; CHECK-NEXT: [[L_J:%.*]] = load ptr, ptr [[GEP_J]], align 8
428437
; CHECK-NEXT: [[CMP3:%.*]] = icmp ult ptr [[L_I]], [[L_J]]
429438
; CHECK-NEXT: [[DEC:%.*]] = zext i1 [[CMP3]] to i64
430-
; CHECK-NEXT: [[J_NEXT]] = sub nsw i64 [[DEC]], [[J]]
431-
; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds ptr, ptr [[DST:%.*]], i64 [[IV]]
432-
; CHECK-NEXT: store i64 [[J_NEXT]], ptr [[GEP_DST]], align 8
433-
; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
434-
; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], [[J_START]]
439+
; CHECK-NEXT: [[CMP3_FROZEN:%.*]] = freeze i1 [[CMP3]]
440+
; CHECK-NEXT: br i1 [[CMP3_FROZEN]], label [[SELECT_TRUE_SINK:%.*]], label [[SELECT_END]]
441+
; CHECK: select.true.sink:
442+
; CHECK-NEXT: [[TMP0:%.*]] = sub nsw i64 1, [[J]]
443+
; CHECK-NEXT: br label [[SELECT_END]]
444+
; CHECK: select.end:
445+
; CHECK-NEXT: [[J_NEXT]] = phi i64 [ [[TMP0]], [[SELECT_TRUE_SINK]] ], [ [[J]], [[LOOP]] ]
446+
; CHECK-NEXT: [[GEP_DST1:%.*]] = getelementptr inbounds ptr, ptr [[DST1:%.*]], i64 [[IV1]]
447+
; CHECK-NEXT: store i64 [[J_NEXT]], ptr [[GEP_DST1]], align 8
448+
; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV1]], 1
449+
; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV1]], [[J_START]]
435450
; CHECK-NEXT: br i1 [[EC]], label [[EXIT:%.*]], label [[LOOP]]
436451
; CHECK: exit:
437452
; CHECK-NEXT: ret void
@@ -465,20 +480,23 @@ define void @test_sub_zext_not(ptr %dst, ptr %src, i64 %j.start, i64 %p, i64 %i.
465480
; CHECK-NEXT: entry:
466481
; CHECK-NEXT: br label [[LOOP:%.*]]
467482
; CHECK: loop:
483+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[SELECT_END:%.*]] ]
484+
; CHECK-NEXT: [[J:%.*]] = phi i64 [ [[J_START:%.*]], [[ENTRY]] ], [ [[J_NEXT:%.*]], [[SELECT_END]] ]
485+
; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[I_START:%.*]], [[ENTRY]] ], [ [[J_NEXT]], [[SELECT_END]] ]
468486
; CHECK-NEXT: [[GEP_I:%.*]] = getelementptr inbounds ptr, ptr [[SRC:%.*]], i64 [[I]]
469487
; CHECK-NEXT: [[L_I:%.*]] = load ptr, ptr [[GEP_I]], align 8
470488
; CHECK-NEXT: [[GEP_J:%.*]] = getelementptr inbounds ptr, ptr [[SRC]], i64 [[J]]
471489
; CHECK-NEXT: [[L_J:%.*]] = load ptr, ptr [[GEP_J]], align 8
472490
; CHECK-NEXT: [[CMP3:%.*]] = icmp ult ptr [[L_I]], [[L_J]]
473491
; CHECK-NEXT: [[NOT_CMP3:%.*]] = xor i1 [[CMP3]], true
474492
; CHECK-NEXT: [[DEC:%.*]] = zext i1 [[NOT_CMP3]] to i64
475-
; CHECK-NEXT: [[NOT_CMP3_FROZEN:%.*]] = freeze i1 [[NOT_CMP3]]
476-
; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[J]], 1
477-
; CHECK-NEXT: br i1 [[NOT_CMP3_FROZEN]], label [[SELECT_END]], label [[SELECT_FALSE:%.*]]
478-
; CHECK: select.false:
493+
; CHECK-NEXT: [[CMP3_FROZEN:%.*]] = freeze i1 [[CMP3]]
494+
; CHECK-NEXT: br i1 [[CMP3_FROZEN]], label [[SELECT_END]], label [[SELECT_FALSE_SINK:%.*]]
495+
; CHECK: select.false.sink:
496+
; CHECK-NEXT: [[TMP0:%.*]] = sub nsw i64 [[J]], 1
479497
; CHECK-NEXT: br label [[SELECT_END]]
480498
; CHECK: select.end:
481-
; CHECK-NEXT: [[J_NEXT]] = phi i64 [ [[TMP0]], [[LOOP]] ], [ [[J]], [[SELECT_FALSE]] ]
499+
; CHECK-NEXT: [[J_NEXT]] = phi i64 [ [[J]], [[LOOP]] ], [ [[TMP0]], [[SELECT_FALSE_SINK]] ]
482500
; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds ptr, ptr [[DST:%.*]], i64 [[IV]]
483501
; CHECK-NEXT: store i64 [[J_NEXT]], ptr [[GEP_DST]], align 8
484502
; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1

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