@@ -91,3 +91,101 @@ define i32 @test_add_and_fptosi() nounwind {
9191 %4 = fptosi fp128 %3 to i32
9292 ret i32 %4
9393}
94+
95+ define fp128 @fmaximum (fp128 %x , fp128 %y ) {
96+ ; RV32I-LABEL: fmaximum:
97+ ; RV32I: # %bb.0:
98+ ; RV32I-NEXT: addi sp, sp, -64
99+ ; RV32I-NEXT: .cfi_def_cfa_offset 64
100+ ; RV32I-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
101+ ; RV32I-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
102+ ; RV32I-NEXT: .cfi_offset ra, -4
103+ ; RV32I-NEXT: .cfi_offset s0, -8
104+ ; RV32I-NEXT: lw a3, 0(a1)
105+ ; RV32I-NEXT: lw a4, 4(a1)
106+ ; RV32I-NEXT: lw a5, 8(a1)
107+ ; RV32I-NEXT: lw a6, 12(a1)
108+ ; RV32I-NEXT: lw a1, 0(a2)
109+ ; RV32I-NEXT: lw a7, 4(a2)
110+ ; RV32I-NEXT: lw t0, 8(a2)
111+ ; RV32I-NEXT: lw a2, 12(a2)
112+ ; RV32I-NEXT: mv s0, a0
113+ ; RV32I-NEXT: sw a1, 8(sp)
114+ ; RV32I-NEXT: sw a7, 12(sp)
115+ ; RV32I-NEXT: sw t0, 16(sp)
116+ ; RV32I-NEXT: sw a2, 20(sp)
117+ ; RV32I-NEXT: addi a0, sp, 40
118+ ; RV32I-NEXT: addi a1, sp, 24
119+ ; RV32I-NEXT: addi a2, sp, 8
120+ ; RV32I-NEXT: sw a3, 24(sp)
121+ ; RV32I-NEXT: sw a4, 28(sp)
122+ ; RV32I-NEXT: sw a5, 32(sp)
123+ ; RV32I-NEXT: sw a6, 36(sp)
124+ ; RV32I-NEXT: call fmaximuml
125+ ; RV32I-NEXT: lw a0, 40(sp)
126+ ; RV32I-NEXT: lw a1, 44(sp)
127+ ; RV32I-NEXT: lw a2, 48(sp)
128+ ; RV32I-NEXT: lw a3, 52(sp)
129+ ; RV32I-NEXT: sw a0, 0(s0)
130+ ; RV32I-NEXT: sw a1, 4(s0)
131+ ; RV32I-NEXT: sw a2, 8(s0)
132+ ; RV32I-NEXT: sw a3, 12(s0)
133+ ; RV32I-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
134+ ; RV32I-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
135+ ; RV32I-NEXT: .cfi_restore ra
136+ ; RV32I-NEXT: .cfi_restore s0
137+ ; RV32I-NEXT: addi sp, sp, 64
138+ ; RV32I-NEXT: .cfi_def_cfa_offset 0
139+ ; RV32I-NEXT: ret
140+ %a = call fp128 @llvm.maximum.fp128 (fp128 %x , fp128 %y )
141+ ret fp128 %a
142+ }
143+
144+ define fp128 @fminimum (fp128 %x , fp128 %y ) {
145+ ; RV32I-LABEL: fminimum:
146+ ; RV32I: # %bb.0:
147+ ; RV32I-NEXT: addi sp, sp, -64
148+ ; RV32I-NEXT: .cfi_def_cfa_offset 64
149+ ; RV32I-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
150+ ; RV32I-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
151+ ; RV32I-NEXT: .cfi_offset ra, -4
152+ ; RV32I-NEXT: .cfi_offset s0, -8
153+ ; RV32I-NEXT: lw a3, 0(a1)
154+ ; RV32I-NEXT: lw a4, 4(a1)
155+ ; RV32I-NEXT: lw a5, 8(a1)
156+ ; RV32I-NEXT: lw a6, 12(a1)
157+ ; RV32I-NEXT: lw a1, 0(a2)
158+ ; RV32I-NEXT: lw a7, 4(a2)
159+ ; RV32I-NEXT: lw t0, 8(a2)
160+ ; RV32I-NEXT: lw a2, 12(a2)
161+ ; RV32I-NEXT: mv s0, a0
162+ ; RV32I-NEXT: sw a1, 8(sp)
163+ ; RV32I-NEXT: sw a7, 12(sp)
164+ ; RV32I-NEXT: sw t0, 16(sp)
165+ ; RV32I-NEXT: sw a2, 20(sp)
166+ ; RV32I-NEXT: addi a0, sp, 40
167+ ; RV32I-NEXT: addi a1, sp, 24
168+ ; RV32I-NEXT: addi a2, sp, 8
169+ ; RV32I-NEXT: sw a3, 24(sp)
170+ ; RV32I-NEXT: sw a4, 28(sp)
171+ ; RV32I-NEXT: sw a5, 32(sp)
172+ ; RV32I-NEXT: sw a6, 36(sp)
173+ ; RV32I-NEXT: call fminimuml
174+ ; RV32I-NEXT: lw a0, 40(sp)
175+ ; RV32I-NEXT: lw a1, 44(sp)
176+ ; RV32I-NEXT: lw a2, 48(sp)
177+ ; RV32I-NEXT: lw a3, 52(sp)
178+ ; RV32I-NEXT: sw a0, 0(s0)
179+ ; RV32I-NEXT: sw a1, 4(s0)
180+ ; RV32I-NEXT: sw a2, 8(s0)
181+ ; RV32I-NEXT: sw a3, 12(s0)
182+ ; RV32I-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
183+ ; RV32I-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
184+ ; RV32I-NEXT: .cfi_restore ra
185+ ; RV32I-NEXT: .cfi_restore s0
186+ ; RV32I-NEXT: addi sp, sp, 64
187+ ; RV32I-NEXT: .cfi_def_cfa_offset 0
188+ ; RV32I-NEXT: ret
189+ %a = call fp128 @llvm.minimum.fp128 (fp128 %x , fp128 %y )
190+ ret fp128 %a
191+ }
0 commit comments