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[RISCV] Enforce even-numbered vd for xsmtvdot.
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6 files changed

+75
-12
lines changed

6 files changed

+75
-12
lines changed

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -283,6 +283,17 @@ static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint32_t RegNo,
283283
return MCDisassembler::Success;
284284
}
285285

286+
static DecodeStatus DecodeVREvenRegisterClass(MCInst &Inst, uint32_t RegNo,
287+
uint64_t Address,
288+
const MCDisassembler *Decoder) {
289+
if (RegNo >= 32 || RegNo % 2)
290+
return MCDisassembler::Fail;
291+
292+
MCRegister Reg = RISCV::V0 + RegNo;
293+
Inst.addOperand(MCOperand::createReg(Reg));
294+
return MCDisassembler::Success;
295+
}
296+
286297
static DecodeStatus DecodeVRM2RegisterClass(MCInst &Inst, uint32_t RegNo,
287298
uint64_t Address,
288299
const MCDisassembler *Decoder) {

‎llvm/lib/Target/RISCV/RISCVInstrInfoXSMTVDot.td‎

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,7 @@ def SMT_VDot_Slide3 : SMTVEncoding2<0b10>;
6161
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
6262
// Base vector dot product (no slide) format.
6363
class RVInstSMTVDot<SMTVEncoding2 sign, string opcodestr, string argstr>
64-
: RVInst<(outs VR:$vd), (ins VR:$vs1, VR:$vs2), opcodestr, argstr, [], InstFormatR> {
64+
: RVInst<(outs VREven:$vd), (ins VR:$vs1, VR:$vs2), opcodestr, argstr, [], InstFormatR> {
6565
bits<5> vd;
6666
bits<5> vs1;
6767
bits<5> vs2;
@@ -78,7 +78,7 @@ class RVInstSMTVDot<SMTVEncoding2 sign, string opcodestr, string argstr>
7878

7979
// Sliding-window vector dot product format.
8080
class RVInstSMTVDotSlide<SMTVEncoding2 funct2, SMTVEncoding2 sign, string opcodestr, string argstr>
81-
: RVInst<(outs VR:$vd), (ins VR:$vs1, VR:$vs2), opcodestr, argstr, [], InstFormatR> {
81+
: RVInst<(outs VREven:$vd), (ins VREven:$vs1, VR:$vs2), opcodestr, argstr, [], InstFormatR> {
8282
bits<5> vd;
8383
bits<5> vs1;
8484
bits<5> vs2;
@@ -104,7 +104,6 @@ let Predicates = [HasVendorXSMTVDot] in {
104104
// Base vector dot product (no slide) instructions
105105
// NOTE: Destination registers (vd) MUST be even-numbered (v0, v2, ..., v30)
106106
// due to hardware alignment constraints. Using odd registers may cause undefined behavior.
107-
// TODO: Enforce even-numbered vd.
108107
def VMADOT : RVInstSMTVDot<SMT_VDot_SS, "smt.vmadot", "$vd, $vs1, $vs2">;
109108
def VMADOTU : RVInstSMTVDot<SMT_VDot_UU, "smt.vmadotu", "$vd, $vs1, $vs2">;
110109
def VMADOTSU : RVInstSMTVDot<SMT_VDot_SU, "smt.vmadotsu", "$vd, $vs1, $vs2">;
@@ -124,7 +123,6 @@ def VMADOTUU : RVInstSMTVDot<SMT_VDot_US, "smt.vmadotus", "$vd, $vs1, $vs2">;
124123
// NOTE: Destination registers (vd) and first source register (vs1) MUST be
125124
// even-numbered (v0, v2, ..., v30) due to hardware alignment constraints.
126125
// Using odd registers may cause undefined behavior.
127-
// TODO: Enforce even-numbered vd.
128126
def VMADOT1 : RVInstSMTVDotSlide<SMT_VDot_Slide1, SMT_VDot_SS, "smt.vmadot1", "$vd, $vs1, $vs2">;
129127
def VMADOT1U : RVInstSMTVDotSlide<SMT_VDot_Slide1, SMT_VDot_UU, "smt.vmadot1u", "$vd, $vs1, $vs2">;
130128
def VMADOT1SU : RVInstSMTVDotSlide<SMT_VDot_Slide1, SMT_VDot_SU, "smt.vmadot1su", "$vd, $vs1, $vs2">;

‎llvm/lib/Target/RISCV/RISCVRegisterInfo.td‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -787,6 +787,8 @@ def VR : VReg<!listconcat(VM1VTs, VMaskVTs),
787787

788788
def VRNoV0 : VReg<!listconcat(VM1VTs, VMaskVTs), (sub VR, V0), 1>;
789789

790+
def VREven : VReg<!listconcat(VM1VTs, VMaskVTs), (add (sequence "V%u", 0, 31, 2)), 1>;
791+
790792
def VRM2 : VReg<VM2VTs, (add (sequence "V%uM2", 8, 31, 2),
791793
(sequence "V%uM2", 6, 0, 2)), 2>;
792794

‎llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1220,9 +1220,9 @@ define void @mgather_nxv16i64(<vscale x 8 x ptr> %ptrs0, <vscale x 8 x ptr> %ptr
12201220
; RV32-LABEL: mgather_nxv16i64:
12211221
; RV32: # %bb.0:
12221222
; RV32-NEXT: vl8re64.v v24, (a0)
1223-
; RV32-NEXT: csrr a0, vlenb
1224-
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
1223+
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
12251224
; RV32-NEXT: vluxei32.v v16, (zero), v8, v0.t
1225+
; RV32-NEXT: csrr a0, vlenb
12261226
; RV32-NEXT: srli a2, a0, 3
12271227
; RV32-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
12281228
; RV32-NEXT: vslidedown.vx v0, v0, a2

‎llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -55,7 +55,7 @@ body: |
5555
; CHECK-NEXT: %pt2:vrm4 = IMPLICIT_DEF
5656
; CHECK-NEXT: [[INIT_UNDEF:%[0-9]+]]:vrm2nov0 = INIT_UNDEF
5757
; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm2_1
58-
; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:vr = INIT_UNDEF
58+
; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:vreven = INIT_UNDEF
5959
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm1_0
6060
; CHECK-NEXT: early-clobber %6:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed [[INSERT_SUBREG2]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
6161
; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
@@ -131,7 +131,7 @@ body: |
131131
; CHECK-NEXT: %pt2:vrm4 = IMPLICIT_DEF
132132
; CHECK-NEXT: [[INIT_UNDEF:%[0-9]+]]:vrm2 = INIT_UNDEF
133133
; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm2_0
134-
; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:vrnov0 = INIT_UNDEF
134+
; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:vreven_and_vrnov0 = INIT_UNDEF
135135
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm1_2
136136
; CHECK-NEXT: early-clobber %6:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed [[INSERT_SUBREG2]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
137137
; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
@@ -284,7 +284,7 @@ body: |
284284
; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm4_1
285285
; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:vrm2nov0 = INIT_UNDEF
286286
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm2_1
287-
; CHECK-NEXT: [[INIT_UNDEF2:%[0-9]+]]:vr = INIT_UNDEF
287+
; CHECK-NEXT: [[INIT_UNDEF2:%[0-9]+]]:vreven = INIT_UNDEF
288288
; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[INIT_UNDEF2]], %subreg.sub_vrm1_0
289289
; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
290290
; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
@@ -364,7 +364,7 @@ body: |
364364
; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm4_1
365365
; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:vrm2 = INIT_UNDEF
366366
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm2_0
367-
; CHECK-NEXT: [[INIT_UNDEF2:%[0-9]+]]:vrnov0 = INIT_UNDEF
367+
; CHECK-NEXT: [[INIT_UNDEF2:%[0-9]+]]:vreven_and_vrnov0 = INIT_UNDEF
368368
; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[INIT_UNDEF2]], %subreg.sub_vrm1_2
369369
; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
370370
; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
@@ -444,7 +444,7 @@ body: |
444444
; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm4_0
445445
; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:vrm2nov0 = INIT_UNDEF
446446
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm2_3
447-
; CHECK-NEXT: [[INIT_UNDEF2:%[0-9]+]]:vrnov0 = INIT_UNDEF
447+
; CHECK-NEXT: [[INIT_UNDEF2:%[0-9]+]]:vreven_and_vrnov0 = INIT_UNDEF
448448
; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[INIT_UNDEF2]], %subreg.sub_vrm1_4
449449
; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
450450
; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
@@ -524,7 +524,7 @@ body: |
524524
; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm4_0
525525
; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:vrm2nov0 = INIT_UNDEF
526526
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm2_2
527-
; CHECK-NEXT: [[INIT_UNDEF2:%[0-9]+]]:vrnov0 = INIT_UNDEF
527+
; CHECK-NEXT: [[INIT_UNDEF2:%[0-9]+]]:vreven_and_vrnov0 = INIT_UNDEF
528528
; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[INIT_UNDEF2]], %subreg.sub_vrm1_6
529529
; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
530530
; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0

‎llvm/test/MC/RISCV/xsmtvdot-invalid.s‎

Lines changed: 52 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,52 @@
1+
# RUN: not llvm-mc -triple riscv32 -mattr=+xsmtvdot < %s 2>&1 \
2+
# RUN: | FileCheck %s
3+
# RUN: not llvm-mc -triple riscv64 -mattr=+xsmtvdot < %s 2>&1 \
4+
# RUN: | FileCheck %s
5+
6+
# NoSlide
7+
smt.vmadot v1, v2, v2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
8+
smt.vmadotu v1, v2, v2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
9+
smt.vmadotsu v1, v2, v2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
10+
smt.vmadotus v1, v2, v2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
11+
12+
# Slide = 1
13+
smt.vmadot1 v1, v2, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
14+
smt.vmadot1u v1, v2, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
15+
smt.vmadot1su v1, v2, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
16+
smt.vmadot1us v1, v2, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
17+
smt.vmadot1 v2, v1, v2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
18+
smt.vmadot1u v2, v1, v2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
19+
smt.vmadot1su v2, v1, v2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
20+
smt.vmadot1us v2, v1, v2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
21+
smt.vmadot1 v1, v3, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
22+
smt.vmadot1u v1, v3, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
23+
smt.vmadot1su v1, v3, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
24+
smt.vmadot1us v1, v3, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
25+
26+
# Slide = 2
27+
smt.vmadot2 v1, v2, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
28+
smt.vmadot2u v1, v2, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
29+
smt.vmadot2su v1, v2, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
30+
smt.vmadot2us v1, v2, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
31+
smt.vmadot2 v2, v1, v2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
32+
smt.vmadot2u v2, v1, v2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
33+
smt.vmadot2su v2, v1, v2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
34+
smt.vmadot2us v2, v1, v2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
35+
smt.vmadot2 v1, v3, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
36+
smt.vmadot2u v1, v3, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
37+
smt.vmadot2su v1, v3, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
38+
smt.vmadot2us v1, v3, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
39+
40+
# Slide = 3
41+
smt.vmadot3 v1, v2, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
42+
smt.vmadot3u v1, v2, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
43+
smt.vmadot3su v1, v2, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
44+
smt.vmadot3us v1, v2, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
45+
smt.vmadot3 v2, v1, v2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
46+
smt.vmadot3u v2, v1, v2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
47+
smt.vmadot3su v2, v1, v2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
48+
smt.vmadot3us v2, v1, v2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
49+
smt.vmadot3 v1, v3, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
50+
smt.vmadot3u v1, v3, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
51+
smt.vmadot3su v1, v3, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
52+
smt.vmadot3us v1, v3, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction

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