Tablegen simple

Author: adam-yang

llvm/include/llvm/IR/IntrinsicsDirectX.td

@@ -93,6 +93,5 @@ def int_dx_splitdouble : DefaultAttrsIntrinsic<[llvm_anyint_ty, LLVMMatchType<0>
     [LLVMScalarOrSameVectorWidth<0, llvm_double_ty>], [IntrNoMem]>;
 def int_dx_radians : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
 
-def int_dx_memory_barrier : DefaultAttrsIntrinsic<[], [llvm_i32_ty], []>;
 def int_dx_group_memory_barrier_with_group_sync : DefaultAttrsIntrinsic<[], [], []>;
 }

llvm/lib/Target/DirectX/DXIL.td

@@ -294,6 +294,11 @@ class Attributes<Version ver = DXIL1_0, list<DXILAttribute> attrs> {
   list<DXILAttribute> op_attrs = attrs;
 }
 
+class IntrinsicSelect<Intrinsic intr, list<string> extra_args> {
+  Intrinsic Intr = intr;
+  list<string> ExtraArgs = extra_args;
+}
+
 // Abstraction DXIL Operation
 class DXILOp<int opcode, DXILOpClass opclass> {
   // A short description of the operation
@@ -308,6 +313,8 @@ class DXILOp<int opcode, DXILOpClass opclass> {
   // LLVM Intrinsic DXIL Operation maps to
   Intrinsic LLVMIntrinsic = ?;
 
+  list<IntrinsicSelect> intrinsic_selects = [];
+
   // Result type of the op
   DXILOpParamType result;
 
@@ -832,7 +839,12 @@ def WaveGetLaneIndex : DXILOp<111, waveGetLaneIndex> {
 
 def Barrier : DXILOp<80, barrier> {
   let Doc = "inserts a memory barrier in the shader";
-  let LLVMIntrinsic = int_dx_memory_barrier;
+  let intrinsic_selects = [
+    IntrinsicSelect<
+        int_dx_group_memory_barrier_with_group_sync,
+        [ "OpBuilder.getIRB().getInt32((unsigned)BarrierMode::SyncThreadGroup | (unsigned)BarrierMode::TGSMFence)" ]>,
+  ];
+
   let arguments = [Int32Ty];
   let result = VoidTy;
   let stages = [Stages<DXIL1_0, [compute, library]>];

llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp

@@ -11,7 +11,6 @@
 //===----------------------------------------------------------------------===//
 
 #include "DXILIntrinsicExpansion.h"
-#include "DXILConstants.h"
 #include "DirectX.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/SmallVector.h"
@@ -67,7 +66,6 @@ static bool isIntrinsicExpansion(Function &F) {
   case Intrinsic::dx_sign:
   case Intrinsic::dx_step:
   case Intrinsic::dx_radians:
-  case Intrinsic::dx_group_memory_barrier_with_group_sync:
     return true;
   }
   return false;
@@ -454,27 +452,6 @@ static Value *expandRadiansIntrinsic(CallInst *Orig) {
   return Builder.CreateFMul(X, PiOver180);
 }
 
-static Value *expandMemoryBarrier(CallInst *Orig, Intrinsic::ID IntrinsicId) {
-  assert(IntrinsicId == Intrinsic::dx_group_memory_barrier_with_group_sync);
-  unsigned BarrierMode = 0;
-  switch (IntrinsicId) {
-  case Intrinsic::dx_group_memory_barrier_with_group_sync:
-    BarrierMode = (unsigned)dxil::BarrierMode::TGSMFence |
-                  (unsigned)dxil::BarrierMode::SyncThreadGroup;
-    break;
-  default:
-    report_fatal_error(Twine("Unexpected memory barrier intrinsic."),
-                       /* gen_crash_diag=*/false);
-    break;
-  }
-
-  IRBuilder<> Builder(Orig);
-  return Builder.CreateIntrinsic(
-      Builder.getVoidTy(), Intrinsic::dx_memory_barrier,
-      ArrayRef<Value *>{Builder.getInt32(BarrierMode)}, nullptr,
-      Orig->getName());
-}
-
 static Intrinsic::ID getMaxForClamp(Type *ElemTy,
                                     Intrinsic::ID ClampIntrinsic) {
   if (ClampIntrinsic == Intrinsic::dx_uclamp)
@@ -609,9 +586,6 @@ static bool expandIntrinsic(Function &F, CallInst *Orig) {
   case Intrinsic::dx_radians:
     Result = expandRadiansIntrinsic(Orig);
     break;
-  case Intrinsic::dx_group_memory_barrier_with_group_sync:
-    Result = expandMemoryBarrier(Orig, IntrinsicId);
-    break;
   }
   if (Result) {
     Orig->replaceAllUsesWith(Result);

llvm/lib/Target/DirectX/DXILOpLowering.cpp

@@ -106,20 +106,21 @@ class OpLowerer {
     return false;
   }
 
-  [[nodiscard]]
-  bool replaceFunctionWithOp(Function &F, dxil::OpCode DXILOp) {
+  [[nodiscard]] bool replaceFunctionWithOp(Function &F, dxil::OpCode DXILOp,
+                                           ArrayRef<Value *> ExtraArgs) {
     bool IsVectorArgExpansion = isVectorArgExpansion(F);
     return replaceFunction(F, [&](CallInst *CI) -> Error {
-      SmallVector<Value *> Args;
-      OpBuilder.getIRB().SetInsertPoint(CI);
+      SmallVector<Value *> NewArgs;
       if (IsVectorArgExpansion) {
-        SmallVector<Value *> NewArgs = argVectorFlatten(CI, OpBuilder.getIRB());
-        Args.append(NewArgs.begin(), NewArgs.end());
+        NewArgs = argVectorFlatten(CI, OpBuilder.getIRB());
       } else
-        Args.append(CI->arg_begin(), CI->arg_end());
+        NewArgs.append(CI->arg_begin(), CI->arg_end());
 
-      Expected<CallInst *> OpCall =
-          OpBuilder.tryCreateOp(DXILOp, Args, CI->getName(), F.getReturnType());
+      NewArgs.append(ExtraArgs.begin(), ExtraArgs.end());
+
+      OpBuilder.getIRB().SetInsertPoint(CI);
+      Expected<CallInst *> OpCall = OpBuilder.tryCreateOp(
+          DXILOp, NewArgs, CI->getName(), F.getReturnType());
       if (Error E = OpCall.takeError())
         return E;
 
@@ -583,9 +584,9 @@ class OpLowerer {
       switch (ID) {
       default:
         continue;
-#define DXIL_OP_INTRINSIC(OpCode, Intrin)                                      \
-  case Intrin:                                                                 \
-    HasErrors |= replaceFunctionWithOp(F, OpCode);                             \
+#define DXIL_OP_INTRINSIC(OpCode, Intrin, ExtraArgs)                         \
+  case Intrin:                                                               \
+    HasErrors |= replaceFunctionWithOp(F, OpCode, ExtraArgs);                \
     break;
 #include "DXILOperation.inc"
       case Intrinsic::dx_handle_fromBinding:

llvm/test/CodeGen/DirectX/group_memory_barrier_with_group_sync.ll

@@ -1,4 +1,4 @@
-; RUN: opt -S -dxil-intrinsic-expansion -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-library < %s | FileCheck %s --check-prefix=CHECK
+; RUN: opt -S -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-library < %s | FileCheck %s --check-prefix=CHECK
 
 define void @test_group_memory_barrier_with_group_sync() {
 entry:

llvm/utils/TableGen/DXILEmitter.cpp

@@ -32,6 +32,11 @@ using namespace llvm::dxil;
 
 namespace {
 
+struct DXILIntrinsicSelect {
+  StringRef Intrinsic;
+  SmallVector<StringRef, 4> ExtraArgs;
+};
+
 struct DXILOperationDesc {
   std::string OpName; // name of DXIL operation
   int OpCode;         // ID of DXIL operation
@@ -42,8 +47,7 @@ struct DXILOperationDesc {
   SmallVector<const Record *> OverloadRecs;
   SmallVector<const Record *> StageRecs;
   SmallVector<const Record *> AttrRecs;
-  StringRef Intrinsic; // The llvm intrinsic map to OpName. Default is "" which
-                       // means no map exists
+  SmallVector<DXILIntrinsicSelect> IntrinsicSelects;
   SmallVector<StringRef, 4>
       ShaderStages; // shader stages to which this applies, empty for all.
   int OverloadParamIndex;             // Index of parameter with overload type.
@@ -157,14 +161,43 @@ DXILOperationDesc::DXILOperationDesc(const Record *R) {
                            OpName);
   }
 
-  const RecordVal *RV = R->getValue("LLVMIntrinsic");
-  if (RV && RV->getValue()) {
-    if (const DefInit *DI = dyn_cast<DefInit>(RV->getValue())) {
-      auto *IntrinsicDef = DI->getDef();
-      auto DefName = IntrinsicDef->getName();
-      assert(DefName.starts_with("int_") && "invalid intrinsic name");
-      // Remove the int_ from intrinsic name.
-      Intrinsic = DefName.substr(4);
+  auto GetIntrinsicName = [](const RecordVal *RV) -> StringRef {
+    if (RV && RV->getValue()) {
+      if (const DefInit *DI = dyn_cast<DefInit>(RV->getValue())) {
+        auto *IntrinsicDef = DI->getDef();
+        auto DefName = IntrinsicDef->getName();
+        assert(DefName.starts_with("int_") && "invalid intrinsic name");
+        // Remove the int_ from intrinsic name.
+        return DefName.substr(4);
+      }
+    }
+    return "";
+  };
+
+  {
+    DXILIntrinsicSelect IntrSelect;
+    IntrSelect.Intrinsic = GetIntrinsicName(R->getValue("LLVMIntrinsic"));
+    if (IntrSelect.Intrinsic.size())
+      IntrinsicSelects.emplace_back(std::move(IntrSelect));
+  }
+
+  Recs = R->getValueAsListOfDefs("intrinsic_selects");
+  if (Recs.size()) {
+    if (IntrinsicSelects.size()) {
+      PrintFatalError(R,
+                      Twine("LLVMIntrinsic and intrinsic_match cannot be both "
+                            "defined for DXIL operation - ") +
+                          OpName);
+    } else {
+      for (const Record *R : Recs) {
+        DXILIntrinsicSelect IntrSelect;
+        IntrSelect.Intrinsic = GetIntrinsicName(R->getValue("Intr"));
+        auto ExtraArgs = R->getValueAsListOfStrings("ExtraArgs");
+        for (StringRef Arg : ExtraArgs) {
+          IntrSelect.ExtraArgs.push_back(Arg);
+        }
+        IntrinsicSelects.emplace_back(std::move(IntrSelect));
+      }
     }
   }
 }
@@ -377,10 +410,17 @@ static void emitDXILIntrinsicMap(ArrayRef<DXILOperationDesc> Ops,
   OS << "#ifdef DXIL_OP_INTRINSIC\n";
   OS << "\n";
   for (const auto &Op : Ops) {
-    if (Op.Intrinsic.empty())
+    if (Op.IntrinsicSelects.empty()) {
       continue;
-    OS << "DXIL_OP_INTRINSIC(dxil::OpCode::" << Op.OpName
-       << ", Intrinsic::" << Op.Intrinsic << ")\n";
+    }
+    for (const DXILIntrinsicSelect &MappedIntr : Op.IntrinsicSelects) {
+      OS << "DXIL_OP_INTRINSIC(dxil::OpCode::" << Op.OpName
+         << ", Intrinsic::" << MappedIntr.Intrinsic << ", (ArrayRef<Value *> {";
+      for (const StringRef &Arg : MappedIntr.ExtraArgs) {
+        OS << Arg << ", ";
+      }
+      OS << "}))\n";
+    }
   }
   OS << "\n";
   OS << "#undef DXIL_OP_INTRINSIC\n";