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!fixup address comments, thanks
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+25
-124
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4 files changed

+25
-124
lines changed

‎llvm/include/llvm/Analysis/IVDescriptors.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -294,7 +294,7 @@ class RecurrenceDescriptor {
294294
/// actual type of the Phi if the recurrence has been type-promoted.
295295
Type *getRecurrenceType() const { return RecurrenceType; }
296296

297-
/// Returns the sentinel value for FindFirstIV &FindLastIV recurrences to
297+
/// Returns the sentinel value for FindFirstIV & FindLastIV recurrences to
298298
/// replace the start value.
299299
Value *getSentinelValue() const {
300300
Type *Ty = StartValue->getType();

‎llvm/lib/Analysis/IVDescriptors.cpp‎

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -726,7 +726,6 @@ RecurrenceDescriptor::isFindIVPattern(RecurKind Kind, Loop *TheLoop,
726726
// The maximum acceptable range for the increasing induction variable,
727727
// called the valid range, will be defined as
728728

729-
const ConstantRange IVRange = SE.getSignedRange(AR);
730729
// Keep the minimum (FindLast) or maximum (FindFirst) value of the
731730
// recurrence type as the sentinel value. The maximum acceptable range for
732731
// the induction variable, called the valid range, will be defined as
@@ -746,9 +745,8 @@ RecurrenceDescriptor::isFindIVPattern(RecurKind Kind, Loop *TheLoop,
746745
ValidRange = ConstantRange::getNonEmpty(Sentinel + 1, Sentinel);
747746
} else {
748747
assert(isFindFirstIVRecurrenceKind(Kind) &&
749-
"Kind must either be a FindLastIV or FindFirstIV");
750-
assert(IsSigned &&
751-
"only FindFirstIV with SMax is supported at the moment");
748+
"Kind must either be FindLastIV or FindFirstIV");
749+
assert(IsSigned && "Only FindFirstIV with SMax is supported currently");
752750
ValidRange =
753751
ConstantRange::getNonEmpty(APInt::getSignedMinValue(NumBits),
754752
APInt::getSignedMaxValue(NumBits) - 1);

‎llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -747,9 +747,8 @@ Value *VPInstruction::generate(VPTransformState &State) {
747747
MinMaxKind = IsSigned ? RecurKind::SMax : RecurKind::UMax;
748748
} else {
749749
assert(RecurrenceDescriptor::isFindFirstIVRecurrenceKind(RK) &&
750-
"Kind must either be a FindLastIV or FindFirstIV");
751-
assert(IsSigned &&
752-
"only FindFirstIV with SMax is supported at the moment");
750+
"Kind must either be FindLastIV or FindFirstIV");
751+
assert(IsSigned && "Only FindFirstIV with SMax is currently supported");
753752
MinMaxKind = RecurKind::SMin;
754753
}
755754
for (unsigned Part = 1; Part < UF; ++Part)

‎llvm/test/Transforms/LoopVectorize/iv-select-cmp-decreasing.ll‎

Lines changed: 20 additions & 116 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 5
2-
; RUN: opt -passes=loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -S < %s | FileCheck --check-prefix=IC1VF4 %s
3-
; RUN: opt -passes=loop-vectorize -force-vector-interleave=4 -force-vector-width=4 -S < %s | FileCheck --check-prefix=IC4VF4 %s
4-
; RUN: opt -passes=loop-vectorize -force-vector-interleave=4 -force-vector-width=1 -S < %s | FileCheck --check-prefix=IC4VF1 %s
2+
; RUN: opt -passes=loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -S < %s | FileCheck --check-prefixes=CHECK,IC1VF4 %s
3+
; RUN: opt -passes=loop-vectorize -force-vector-interleave=4 -force-vector-width=4 -S < %s | FileCheck --check-prefixes=CHECK,IC4VF4 %s
4+
; RUN: opt -passes=loop-vectorize -force-vector-interleave=4 -force-vector-width=1 -S < %s | FileCheck --check-prefixes=CHECK,IC4VF1 %s
55

66
define i64 @select_decreasing_induction_icmp_const_start(ptr %a) {
77
; IC1VF4-LABEL: define i64 @select_decreasing_induction_icmp_const_start(
@@ -962,66 +962,6 @@ define i64 @not_vectorized_select_decreasing_induction_icmp_non_const_start(ptr
962962
; CHECK-NEXT: [[COND_LCSSA:%.*]] = phi i64 [ [[COND]], %[[LOOP]] ]
963963
; CHECK-NEXT: ret i64 [[COND_LCSSA]]
964964
;
965-
; IC1VF4-LABEL: define i64 @not_vectorized_select_decreasing_induction_icmp_non_const_start(
966-
; IC1VF4-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[RDX_START:%.*]], i64 [[N:%.*]]) {
967-
; IC1VF4-NEXT: [[ENTRY:.*]]:
968-
; IC1VF4-NEXT: br label %[[LOOP:.*]]
969-
; IC1VF4: [[LOOP]]:
970-
; IC1VF4-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[LOOP]] ], [ [[N]], %[[ENTRY]] ]
971-
; IC1VF4-NEXT: [[RDX:%.*]] = phi i64 [ [[COND:%.*]], %[[LOOP]] ], [ [[RDX_START]], %[[ENTRY]] ]
972-
; IC1VF4-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], -1
973-
; IC1VF4-NEXT: [[GEP_A_IV:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV_NEXT]]
974-
; IC1VF4-NEXT: [[LD_A:%.*]] = load i64, ptr [[GEP_A_IV]], align 8
975-
; IC1VF4-NEXT: [[GEP_B_IV:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[IV_NEXT]]
976-
; IC1VF4-NEXT: [[LD_B:%.*]] = load i64, ptr [[GEP_B_IV]], align 8
977-
; IC1VF4-NEXT: [[CMP_A_B:%.*]] = icmp sgt i64 [[LD_A]], [[LD_B]]
978-
; IC1VF4-NEXT: [[COND]] = select i1 [[CMP_A_B]], i64 [[IV_NEXT]], i64 [[RDX]]
979-
; IC1VF4-NEXT: [[EXIT_COND:%.*]] = icmp ugt i64 [[IV]], 1
980-
; IC1VF4-NEXT: br i1 [[EXIT_COND]], label %[[LOOP]], label %[[EXIT:.*]]
981-
; IC1VF4: [[EXIT]]:
982-
; IC1VF4-NEXT: [[COND_LCSSA:%.*]] = phi i64 [ [[COND]], %[[LOOP]] ]
983-
; IC1VF4-NEXT: ret i64 [[COND_LCSSA]]
984-
;
985-
; IC4VF4-LABEL: define i64 @not_vectorized_select_decreasing_induction_icmp_non_const_start(
986-
; IC4VF4-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[RDX_START:%.*]], i64 [[N:%.*]]) {
987-
; IC4VF4-NEXT: [[ENTRY:.*]]:
988-
; IC4VF4-NEXT: br label %[[LOOP:.*]]
989-
; IC4VF4: [[LOOP]]:
990-
; IC4VF4-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[LOOP]] ], [ [[N]], %[[ENTRY]] ]
991-
; IC4VF4-NEXT: [[RDX:%.*]] = phi i64 [ [[COND:%.*]], %[[LOOP]] ], [ [[RDX_START]], %[[ENTRY]] ]
992-
; IC4VF4-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], -1
993-
; IC4VF4-NEXT: [[GEP_A_IV:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV_NEXT]]
994-
; IC4VF4-NEXT: [[LD_A:%.*]] = load i64, ptr [[GEP_A_IV]], align 8
995-
; IC4VF4-NEXT: [[GEP_B_IV:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[IV_NEXT]]
996-
; IC4VF4-NEXT: [[LD_B:%.*]] = load i64, ptr [[GEP_B_IV]], align 8
997-
; IC4VF4-NEXT: [[CMP_A_B:%.*]] = icmp sgt i64 [[LD_A]], [[LD_B]]
998-
; IC4VF4-NEXT: [[COND]] = select i1 [[CMP_A_B]], i64 [[IV_NEXT]], i64 [[RDX]]
999-
; IC4VF4-NEXT: [[EXIT_COND:%.*]] = icmp ugt i64 [[IV]], 1
1000-
; IC4VF4-NEXT: br i1 [[EXIT_COND]], label %[[LOOP]], label %[[EXIT:.*]]
1001-
; IC4VF4: [[EXIT]]:
1002-
; IC4VF4-NEXT: [[COND_LCSSA:%.*]] = phi i64 [ [[COND]], %[[LOOP]] ]
1003-
; IC4VF4-NEXT: ret i64 [[COND_LCSSA]]
1004-
;
1005-
; IC4VF1-LABEL: define i64 @not_vectorized_select_decreasing_induction_icmp_non_const_start(
1006-
; IC4VF1-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[RDX_START:%.*]], i64 [[N:%.*]]) {
1007-
; IC4VF1-NEXT: [[ENTRY:.*]]:
1008-
; IC4VF1-NEXT: br label %[[LOOP:.*]]
1009-
; IC4VF1: [[LOOP]]:
1010-
; IC4VF1-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[LOOP]] ], [ [[N]], %[[ENTRY]] ]
1011-
; IC4VF1-NEXT: [[RDX:%.*]] = phi i64 [ [[COND:%.*]], %[[LOOP]] ], [ [[RDX_START]], %[[ENTRY]] ]
1012-
; IC4VF1-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], -1
1013-
; IC4VF1-NEXT: [[GEP_A_IV:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV_NEXT]]
1014-
; IC4VF1-NEXT: [[LD_A:%.*]] = load i64, ptr [[GEP_A_IV]], align 8
1015-
; IC4VF1-NEXT: [[GEP_B_IV:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[IV_NEXT]]
1016-
; IC4VF1-NEXT: [[LD_B:%.*]] = load i64, ptr [[GEP_B_IV]], align 8
1017-
; IC4VF1-NEXT: [[CMP_A_B:%.*]] = icmp sgt i64 [[LD_A]], [[LD_B]]
1018-
; IC4VF1-NEXT: [[COND]] = select i1 [[CMP_A_B]], i64 [[IV_NEXT]], i64 [[RDX]]
1019-
; IC4VF1-NEXT: [[EXIT_COND:%.*]] = icmp ugt i64 [[IV]], 1
1020-
; IC4VF1-NEXT: br i1 [[EXIT_COND]], label %[[LOOP]], label %[[EXIT:.*]]
1021-
; IC4VF1: [[EXIT]]:
1022-
; IC4VF1-NEXT: [[COND_LCSSA:%.*]] = phi i64 [ [[COND]], %[[LOOP]] ]
1023-
; IC4VF1-NEXT: ret i64 [[COND_LCSSA]]
1024-
;
1025965
entry:
1026966
br label %loop
1027967

@@ -1045,59 +985,23 @@ exit: ; preds = %loop
1045985
; The sentinel value for decreasing-IV vectorization is LONG_MAX, and since
1046986
; the IV hits this value, it is impossible to vectorize this case.
1047987
define i64 @not_vectorized_select_decreasing_induction_icmp_iv_out_of_bound(ptr %a) {
1048-
; IC1VF4-LABEL: define i64 @not_vectorized_select_decreasing_induction_icmp_iv_out_of_bound(
1049-
; IC1VF4-SAME: ptr [[A:%.*]]) {
1050-
; IC1VF4-NEXT: [[ENTRY:.*]]:
1051-
; IC1VF4-NEXT: br label %[[LOOP:.*]]
1052-
; IC1VF4: [[LOOP]]:
1053-
; IC1VF4-NEXT: [[IV:%.*]] = phi i64 [ 9223372036854775807, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
1054-
; IC1VF4-NEXT: [[RDX:%.*]] = phi i64 [ 331, %[[ENTRY]] ], [ [[SPEC_SELECT:%.*]], %[[LOOP]] ]
1055-
; IC1VF4-NEXT: [[GEP_A_IV:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]]
1056-
; IC1VF4-NEXT: [[LD_A:%.*]] = load i64, ptr [[GEP_A_IV]], align 8
1057-
; IC1VF4-NEXT: [[CMP_A_3:%.*]] = icmp sgt i64 [[LD_A]], 3
1058-
; IC1VF4-NEXT: [[SPEC_SELECT]] = select i1 [[CMP_A_3]], i64 [[IV]], i64 [[RDX]]
1059-
; IC1VF4-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], -1
1060-
; IC1VF4-NEXT: [[EXIT_COND:%.*]] = icmp eq i64 [[IV]], 0
1061-
; IC1VF4-NEXT: br i1 [[EXIT_COND]], label %[[EXIT:.*]], label %[[LOOP]]
1062-
; IC1VF4: [[EXIT]]:
1063-
; IC1VF4-NEXT: [[SPEC_SELECT_LCSSA:%.*]] = phi i64 [ [[SPEC_SELECT]], %[[LOOP]] ]
1064-
; IC1VF4-NEXT: ret i64 [[SPEC_SELECT_LCSSA]]
1065-
;
1066-
; IC4VF4-LABEL: define i64 @not_vectorized_select_decreasing_induction_icmp_iv_out_of_bound(
1067-
; IC4VF4-SAME: ptr [[A:%.*]]) {
1068-
; IC4VF4-NEXT: [[ENTRY:.*]]:
1069-
; IC4VF4-NEXT: br label %[[LOOP:.*]]
1070-
; IC4VF4: [[LOOP]]:
1071-
; IC4VF4-NEXT: [[IV:%.*]] = phi i64 [ 9223372036854775807, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
1072-
; IC4VF4-NEXT: [[RDX:%.*]] = phi i64 [ 331, %[[ENTRY]] ], [ [[SPEC_SELECT:%.*]], %[[LOOP]] ]
1073-
; IC4VF4-NEXT: [[GEP_A_IV:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]]
1074-
; IC4VF4-NEXT: [[LD_A:%.*]] = load i64, ptr [[GEP_A_IV]], align 8
1075-
; IC4VF4-NEXT: [[CMP_A_3:%.*]] = icmp sgt i64 [[LD_A]], 3
1076-
; IC4VF4-NEXT: [[SPEC_SELECT]] = select i1 [[CMP_A_3]], i64 [[IV]], i64 [[RDX]]
1077-
; IC4VF4-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], -1
1078-
; IC4VF4-NEXT: [[EXIT_COND:%.*]] = icmp eq i64 [[IV]], 0
1079-
; IC4VF4-NEXT: br i1 [[EXIT_COND]], label %[[EXIT:.*]], label %[[LOOP]]
1080-
; IC4VF4: [[EXIT]]:
1081-
; IC4VF4-NEXT: [[SPEC_SELECT_LCSSA:%.*]] = phi i64 [ [[SPEC_SELECT]], %[[LOOP]] ]
1082-
; IC4VF4-NEXT: ret i64 [[SPEC_SELECT_LCSSA]]
1083-
;
1084-
; IC4VF1-LABEL: define i64 @not_vectorized_select_decreasing_induction_icmp_iv_out_of_bound(
1085-
; IC4VF1-SAME: ptr [[A:%.*]]) {
1086-
; IC4VF1-NEXT: [[ENTRY:.*]]:
1087-
; IC4VF1-NEXT: br label %[[LOOP:.*]]
1088-
; IC4VF1: [[LOOP]]:
1089-
; IC4VF1-NEXT: [[IV:%.*]] = phi i64 [ 9223372036854775807, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
1090-
; IC4VF1-NEXT: [[RDX:%.*]] = phi i64 [ 331, %[[ENTRY]] ], [ [[SPEC_SELECT:%.*]], %[[LOOP]] ]
1091-
; IC4VF1-NEXT: [[GEP_A_IV:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]]
1092-
; IC4VF1-NEXT: [[LD_A:%.*]] = load i64, ptr [[GEP_A_IV]], align 8
1093-
; IC4VF1-NEXT: [[CMP_A_3:%.*]] = icmp sgt i64 [[LD_A]], 3
1094-
; IC4VF1-NEXT: [[SPEC_SELECT]] = select i1 [[CMP_A_3]], i64 [[IV]], i64 [[RDX]]
1095-
; IC4VF1-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], -1
1096-
; IC4VF1-NEXT: [[EXIT_COND:%.*]] = icmp eq i64 [[IV]], 0
1097-
; IC4VF1-NEXT: br i1 [[EXIT_COND]], label %[[EXIT:.*]], label %[[LOOP]]
1098-
; IC4VF1: [[EXIT]]:
1099-
; IC4VF1-NEXT: [[SPEC_SELECT_LCSSA:%.*]] = phi i64 [ [[SPEC_SELECT]], %[[LOOP]] ]
1100-
; IC4VF1-NEXT: ret i64 [[SPEC_SELECT_LCSSA]]
988+
; CHECK-LABEL: define i64 @not_vectorized_select_decreasing_induction_icmp_iv_out_of_bound(
989+
; CHECK-SAME: ptr [[A:%.*]]) {
990+
; CHECK-NEXT: [[ENTRY:.*]]:
991+
; CHECK-NEXT: br label %[[LOOP:.*]]
992+
; CHECK: [[LOOP]]:
993+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 9223372036854775807, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
994+
; CHECK-NEXT: [[RDX:%.*]] = phi i64 [ 331, %[[ENTRY]] ], [ [[SPEC_SELECT:%.*]], %[[LOOP]] ]
995+
; CHECK-NEXT: [[GEP_A_IV:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]]
996+
; CHECK-NEXT: [[LD_A:%.*]] = load i64, ptr [[GEP_A_IV]], align 8
997+
; CHECK-NEXT: [[CMP_A_3:%.*]] = icmp sgt i64 [[LD_A]], 3
998+
; CHECK-NEXT: [[SPEC_SELECT]] = select i1 [[CMP_A_3]], i64 [[IV]], i64 [[RDX]]
999+
; CHECK-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], -1
1000+
; CHECK-NEXT: [[EXIT_COND:%.*]] = icmp eq i64 [[IV]], 0
1001+
; CHECK-NEXT: br i1 [[EXIT_COND]], label %[[EXIT:.*]], label %[[LOOP]]
1002+
; CHECK: [[EXIT]]:
1003+
; CHECK-NEXT: [[SPEC_SELECT_LCSSA:%.*]] = phi i64 [ [[SPEC_SELECT]], %[[LOOP]] ]
1004+
; CHECK-NEXT: ret i64 [[SPEC_SELECT_LCSSA]]
11011005
;
11021006
entry:
11031007
br label %loop

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