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[LoongArch] Fix instruction selection failure for BUILD_VECTOR on LA32
1 parent 14f2531 commit 3dcf17d

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3 files changed

+147
-30
lines changed

3 files changed

+147
-30
lines changed

‎llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2671,8 +2671,9 @@ SDValue LoongArchTargetLowering::lowerBUILD_VECTOR(SDValue Op,
26712671

26722672
if (SplatBitSize == 64 && !Subtarget.is64Bit()) {
26732673
// We can only handle 64-bit elements that are within
2674-
// the signed 32-bit range on 32-bit targets.
2675-
if (!SplatValue.isSignedIntN(32))
2674+
// the signed 10-bit range on 32-bit targets.
2675+
// See the BUILD_VECTOR case in LoongArchDAGToDAGISel::Select().
2676+
if (!SplatValue.isSignedIntN(10))
26762677
return SDValue();
26772678
if ((Is128Vec && ResTy == MVT::v4i32) ||
26782679
(Is256Vec && ResTy == MVT::v8i32))

‎llvm/test/CodeGen/LoongArch/lasx/build-vector.ll‎

Lines changed: 72 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -106,6 +106,26 @@ entry:
106106
ret void
107107
}
108108

109+
define void @buildvector_v32i8_const_splat_v4i64(ptr %dst) nounwind {
110+
; LA32-LABEL: buildvector_v32i8_const_splat_v4i64:
111+
; LA32: # %bb.0: # %entry
112+
; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI7_0)
113+
; LA32-NEXT: xvld $xr0, $a1, %pc_lo12(.LCPI7_0)
114+
; LA32-NEXT: xvst $xr0, $a0, 0
115+
; LA32-NEXT: ret
116+
;
117+
; LA64-LABEL: buildvector_v32i8_const_splat_v4i64:
118+
; LA64: # %bb.0: # %entry
119+
; LA64-NEXT: lu12i.w $a1, 7
120+
; LA64-NEXT: ori $a1, $a1, 3453
121+
; LA64-NEXT: xvreplgr2vr.d $xr0, $a1
122+
; LA64-NEXT: xvst $xr0, $a0, 0
123+
; LA64-NEXT: ret
124+
entry:
125+
store <32 x i8> <i8 125, i8 125, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 125, i8 125, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 125, i8 125, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 125, i8 125, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, ptr %dst
126+
ret void
127+
}
128+
109129
define void @buildvector_v16i16_const_splat(ptr %dst) nounwind {
110130
; CHECK-LABEL: buildvector_v16i16_const_splat:
111131
; CHECK: # %bb.0: # %entry
@@ -117,6 +137,25 @@ entry:
117137
ret void
118138
}
119139

140+
define void @buildvector_v16i16_const_splat_v4i64(ptr %dst) nounwind {
141+
; LA32-LABEL: buildvector_v16i16_const_splat_v4i64:
142+
; LA32: # %bb.0: # %entry
143+
; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI9_0)
144+
; LA32-NEXT: xvld $xr0, $a1, %pc_lo12(.LCPI9_0)
145+
; LA32-NEXT: xvst $xr0, $a0, 0
146+
; LA32-NEXT: ret
147+
;
148+
; LA64-LABEL: buildvector_v16i16_const_splat_v4i64:
149+
; LA64: # %bb.0: # %entry
150+
; LA64-NEXT: ori $a1, $zero, 512
151+
; LA64-NEXT: xvreplgr2vr.d $xr0, $a1
152+
; LA64-NEXT: xvst $xr0, $a0, 0
153+
; LA64-NEXT: ret
154+
entry:
155+
store <16 x i16> <i16 512, i16 0, i16 0, i16 0, i16 512, i16 0, i16 0, i16 0, i16 512, i16 0, i16 0, i16 0, i16 512, i16 0, i16 0, i16 0>, ptr %dst
156+
ret void
157+
}
158+
120159
define void @buildvector_v8i32_const_splat(ptr %dst) nounwind {
121160
; CHECK-LABEL: buildvector_v8i32_const_splat:
122161
; CHECK: # %bb.0: # %entry
@@ -128,6 +167,25 @@ entry:
128167
ret void
129168
}
130169

170+
define void @buildvector_v8i32_const_splat_v4i64(ptr %dst) nounwind {
171+
; LA32-LABEL: buildvector_v8i32_const_splat_v4i64:
172+
; LA32: # %bb.0: # %entry
173+
; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI11_0)
174+
; LA32-NEXT: xvld $xr0, $a1, %pc_lo12(.LCPI11_0)
175+
; LA32-NEXT: xvst $xr0, $a0, 0
176+
; LA32-NEXT: ret
177+
;
178+
; LA64-LABEL: buildvector_v8i32_const_splat_v4i64:
179+
; LA64: # %bb.0: # %entry
180+
; LA64-NEXT: ori $a1, $zero, 512
181+
; LA64-NEXT: xvreplgr2vr.d $xr0, $a1
182+
; LA64-NEXT: xvst $xr0, $a0, 0
183+
; LA64-NEXT: ret
184+
entry:
185+
store <8 x i32> <i32 512, i32 0, i32 512, i32 0, i32 512, i32 0, i32 512, i32 0>, ptr %dst
186+
ret void
187+
}
188+
131189
define void @buildvector_v4i64_const_splat(ptr %dst) nounwind {
132190
; CHECK-LABEL: buildvector_v4i64_const_splat:
133191
; CHECK: # %bb.0: # %entry
@@ -154,8 +212,8 @@ entry:
154212
define void @buildvector_v4f64_const_splat(ptr %dst) nounwind {
155213
; LA32-LABEL: buildvector_v4f64_const_splat:
156214
; LA32: # %bb.0: # %entry
157-
; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI11_0)
158-
; LA32-NEXT: xvld $xr0, $a1, %pc_lo12(.LCPI11_0)
215+
; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI14_0)
216+
; LA32-NEXT: xvld $xr0, $a1, %pc_lo12(.LCPI14_0)
159217
; LA32-NEXT: xvst $xr0, $a0, 0
160218
; LA32-NEXT: ret
161219
;
@@ -173,8 +231,8 @@ entry:
173231
define void @buildvector_v32i8_const(ptr %dst) nounwind {
174232
; CHECK-LABEL: buildvector_v32i8_const:
175233
; CHECK: # %bb.0: # %entry
176-
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI12_0)
177-
; CHECK-NEXT: xvld $xr0, $a1, %pc_lo12(.LCPI12_0)
234+
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI15_0)
235+
; CHECK-NEXT: xvld $xr0, $a1, %pc_lo12(.LCPI15_0)
178236
; CHECK-NEXT: xvst $xr0, $a0, 0
179237
; CHECK-NEXT: ret
180238
entry:
@@ -185,8 +243,8 @@ entry:
185243
define void @buildvector_v16i16_const(ptr %dst) nounwind {
186244
; CHECK-LABEL: buildvector_v16i16_const:
187245
; CHECK: # %bb.0: # %entry
188-
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI13_0)
189-
; CHECK-NEXT: xvld $xr0, $a1, %pc_lo12(.LCPI13_0)
246+
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI16_0)
247+
; CHECK-NEXT: xvld $xr0, $a1, %pc_lo12(.LCPI16_0)
190248
; CHECK-NEXT: xvst $xr0, $a0, 0
191249
; CHECK-NEXT: ret
192250
entry:
@@ -197,8 +255,8 @@ entry:
197255
define void @buildvector_v8i32_const(ptr %dst) nounwind {
198256
; CHECK-LABEL: buildvector_v8i32_const:
199257
; CHECK: # %bb.0: # %entry
200-
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI14_0)
201-
; CHECK-NEXT: xvld $xr0, $a1, %pc_lo12(.LCPI14_0)
258+
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI17_0)
259+
; CHECK-NEXT: xvld $xr0, $a1, %pc_lo12(.LCPI17_0)
202260
; CHECK-NEXT: xvst $xr0, $a0, 0
203261
; CHECK-NEXT: ret
204262
entry:
@@ -209,8 +267,8 @@ entry:
209267
define void @buildvector_v4i64_const(ptr %dst) nounwind {
210268
; CHECK-LABEL: buildvector_v4i64_const:
211269
; CHECK: # %bb.0: # %entry
212-
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI15_0)
213-
; CHECK-NEXT: xvld $xr0, $a1, %pc_lo12(.LCPI15_0)
270+
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI18_0)
271+
; CHECK-NEXT: xvld $xr0, $a1, %pc_lo12(.LCPI18_0)
214272
; CHECK-NEXT: xvst $xr0, $a0, 0
215273
; CHECK-NEXT: ret
216274
entry:
@@ -221,8 +279,8 @@ entry:
221279
define void @buildvector_v2f32_const(ptr %dst) nounwind {
222280
; CHECK-LABEL: buildvector_v2f32_const:
223281
; CHECK: # %bb.0: # %entry
224-
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI16_0)
225-
; CHECK-NEXT: xvld $xr0, $a1, %pc_lo12(.LCPI16_0)
282+
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI19_0)
283+
; CHECK-NEXT: xvld $xr0, $a1, %pc_lo12(.LCPI19_0)
226284
; CHECK-NEXT: xvst $xr0, $a0, 0
227285
; CHECK-NEXT: ret
228286
entry:
@@ -233,8 +291,8 @@ entry:
233291
define void @buildvector_v4f64_const(ptr %dst) nounwind {
234292
; CHECK-LABEL: buildvector_v4f64_const:
235293
; CHECK: # %bb.0: # %entry
236-
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI17_0)
237-
; CHECK-NEXT: xvld $xr0, $a1, %pc_lo12(.LCPI17_0)
294+
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI20_0)
295+
; CHECK-NEXT: xvld $xr0, $a1, %pc_lo12(.LCPI20_0)
238296
; CHECK-NEXT: xvst $xr0, $a0, 0
239297
; CHECK-NEXT: ret
240298
entry:

‎llvm/test/CodeGen/LoongArch/lsx/build-vector.ll‎

Lines changed: 72 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -102,6 +102,26 @@ entry:
102102
ret void
103103
}
104104

105+
define void @buildvector_v16i8_const_splat_v2i64(ptr %dst) nounwind {
106+
; LA32-LABEL: buildvector_v16i8_const_splat_v2i64:
107+
; LA32: # %bb.0: # %entry
108+
; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI7_0)
109+
; LA32-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI7_0)
110+
; LA32-NEXT: vst $vr0, $a0, 0
111+
; LA32-NEXT: ret
112+
;
113+
; LA64-LABEL: buildvector_v16i8_const_splat_v2i64:
114+
; LA64: # %bb.0: # %entry
115+
; LA64-NEXT: lu12i.w $a1, 7
116+
; LA64-NEXT: ori $a1, $a1, 3453
117+
; LA64-NEXT: vreplgr2vr.d $vr0, $a1
118+
; LA64-NEXT: vst $vr0, $a0, 0
119+
; LA64-NEXT: ret
120+
entry:
121+
store <16 x i8> <i8 125, i8 125, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 125, i8 125, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, ptr %dst
122+
ret void
123+
}
124+
105125
define void @buildvector_v8i16_const_splat(ptr %dst) nounwind {
106126
; CHECK-LABEL: buildvector_v8i16_const_splat:
107127
; CHECK: # %bb.0: # %entry
@@ -113,6 +133,25 @@ entry:
113133
ret void
114134
}
115135

136+
define void @buildvector_v8i16_const_splat_v2i64(ptr %dst) nounwind {
137+
; LA32-LABEL: buildvector_v8i16_const_splat_v2i64:
138+
; LA32: # %bb.0: # %entry
139+
; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI9_0)
140+
; LA32-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI9_0)
141+
; LA32-NEXT: vst $vr0, $a0, 0
142+
; LA32-NEXT: ret
143+
;
144+
; LA64-LABEL: buildvector_v8i16_const_splat_v2i64:
145+
; LA64: # %bb.0: # %entry
146+
; LA64-NEXT: ori $a1, $zero, 512
147+
; LA64-NEXT: vreplgr2vr.d $vr0, $a1
148+
; LA64-NEXT: vst $vr0, $a0, 0
149+
; LA64-NEXT: ret
150+
entry:
151+
store <8 x i16> <i16 512, i16 0, i16 0, i16 0, i16 512, i16 0, i16 0, i16 0>, ptr %dst
152+
ret void
153+
}
154+
116155
define void @buildvector_v4i32_const_splat(ptr %dst) nounwind {
117156
; CHECK-LABEL: buildvector_v4i32_const_splat:
118157
; CHECK: # %bb.0: # %entry
@@ -124,6 +163,25 @@ entry:
124163
ret void
125164
}
126165

166+
define void @buildvector_v4i32_const_splat_v2i64(ptr %dst) nounwind {
167+
; LA32-LABEL: buildvector_v4i32_const_splat_v2i64:
168+
; LA32: # %bb.0: # %entry
169+
; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI11_0)
170+
; LA32-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI11_0)
171+
; LA32-NEXT: vst $vr0, $a0, 0
172+
; LA32-NEXT: ret
173+
;
174+
; LA64-LABEL: buildvector_v4i32_const_splat_v2i64:
175+
; LA64: # %bb.0: # %entry
176+
; LA64-NEXT: ori $a1, $zero, 512
177+
; LA64-NEXT: vreplgr2vr.d $vr0, $a1
178+
; LA64-NEXT: vst $vr0, $a0, 0
179+
; LA64-NEXT: ret
180+
entry:
181+
store <4 x i32> <i32 512, i32 0, i32 512, i32 0>, ptr %dst
182+
ret void
183+
}
184+
127185
define void @buildvector_v2i64_const_splat(ptr %dst) nounwind {
128186
; CHECK-LABEL: buildvector_v2i64_const_splat:
129187
; CHECK: # %bb.0: # %entry
@@ -150,8 +208,8 @@ entry:
150208
define void @buildvector_v2f64_const_splat(ptr %dst) nounwind {
151209
; LA32-LABEL: buildvector_v2f64_const_splat:
152210
; LA32: # %bb.0: # %entry
153-
; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI11_0)
154-
; LA32-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI11_0)
211+
; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI14_0)
212+
; LA32-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI14_0)
155213
; LA32-NEXT: vst $vr0, $a0, 0
156214
; LA32-NEXT: ret
157215
;
@@ -169,8 +227,8 @@ entry:
169227
define void @buildvector_v16i8_const(ptr %dst) nounwind {
170228
; CHECK-LABEL: buildvector_v16i8_const:
171229
; CHECK: # %bb.0: # %entry
172-
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI12_0)
173-
; CHECK-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI12_0)
230+
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI15_0)
231+
; CHECK-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI15_0)
174232
; CHECK-NEXT: vst $vr0, $a0, 0
175233
; CHECK-NEXT: ret
176234
entry:
@@ -181,8 +239,8 @@ entry:
181239
define void @buildvector_v8i16_const(ptr %dst) nounwind {
182240
; CHECK-LABEL: buildvector_v8i16_const:
183241
; CHECK: # %bb.0: # %entry
184-
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI13_0)
185-
; CHECK-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI13_0)
242+
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI16_0)
243+
; CHECK-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI16_0)
186244
; CHECK-NEXT: vst $vr0, $a0, 0
187245
; CHECK-NEXT: ret
188246
entry:
@@ -193,8 +251,8 @@ entry:
193251
define void @buildvector_v4i32_const(ptr %dst) nounwind {
194252
; CHECK-LABEL: buildvector_v4i32_const:
195253
; CHECK: # %bb.0: # %entry
196-
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI14_0)
197-
; CHECK-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI14_0)
254+
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI17_0)
255+
; CHECK-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI17_0)
198256
; CHECK-NEXT: vst $vr0, $a0, 0
199257
; CHECK-NEXT: ret
200258
entry:
@@ -205,8 +263,8 @@ entry:
205263
define void @buildvector_v2i64_const(ptr %dst) nounwind {
206264
; CHECK-LABEL: buildvector_v2i64_const:
207265
; CHECK: # %bb.0: # %entry
208-
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI15_0)
209-
; CHECK-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI15_0)
266+
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI18_0)
267+
; CHECK-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI18_0)
210268
; CHECK-NEXT: vst $vr0, $a0, 0
211269
; CHECK-NEXT: ret
212270
entry:
@@ -217,8 +275,8 @@ entry:
217275
define void @buildvector_v2f32_const(ptr %dst) nounwind {
218276
; CHECK-LABEL: buildvector_v2f32_const:
219277
; CHECK: # %bb.0: # %entry
220-
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI16_0)
221-
; CHECK-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI16_0)
278+
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI19_0)
279+
; CHECK-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI19_0)
222280
; CHECK-NEXT: vst $vr0, $a0, 0
223281
; CHECK-NEXT: ret
224282
entry:
@@ -229,8 +287,8 @@ entry:
229287
define void @buildvector_v2f64_const(ptr %dst) nounwind {
230288
; CHECK-LABEL: buildvector_v2f64_const:
231289
; CHECK: # %bb.0: # %entry
232-
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI17_0)
233-
; CHECK-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI17_0)
290+
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI20_0)
291+
; CHECK-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI20_0)
234292
; CHECK-NEXT: vst $vr0, $a0, 0
235293
; CHECK-NEXT: ret
236294
entry:

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