[GISel] Teach computeKnownBitsImpl to handle COPY instructions that change bit width.

The selectShiftMask ComplexRenderFn on RISCV calls computeKnownBits.

I encountered a case where we looked through a G_PHI and found a
COPY that was created from an already selected G_ANYEXT from s32 to
s64. s32 and s64 integers on RISC-V end up in the same register class.a
The input to the COPY was an already selected s32 SELECT instruction.
We need an s32 SELECT to be legal to support f32 selects. If it isn't
used by FP operations, regbank select will assign to GPR.

This patch uses KnownBits::anyextOrTrunc to adjust the width when
they mismatch.

I haven't reduced a test case yet, but wanted to make sure this is
the right fix.

Author: topperc

llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp

@@ -253,6 +253,7 @@ void GISelKnownBits::computeKnownBitsImpl(Register R, KnownBits &Known,
         // For COPYs we don't do anything, don't increase the depth.
         computeKnownBitsImpl(SrcReg, Known2, DemandedElts,
                              Depth + (Opcode != TargetOpcode::COPY));
+        Known2 = Known2.anyextOrTrunc(BitWidth);
         Known = Known.intersectWith(Known2);
         // If we reach a point where we don't know anything
         // just stop looking through the operands.

llvm/test/CodeGen/RISCV/GlobalISel/knownbits-copy-crash.mir

@@ -0,0 +1,36 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc %s -mtriple=riscv64 -mattr=+zbb,+f -run-pass=instruction-select | FileCheck %s
+
+---
+name:            foo
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: foo
+  ; CHECK: bb.0:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $x0
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, %6, %bb.1
+  ; CHECK-NEXT:   [[ADDIW:%[0-9]+]]:gpr = ADDIW [[PHI]], 0
+  ; CHECK-NEXT:   [[FCVT_S_W:%[0-9]+]]:fpr32 = nofpexcept FCVT_S_W [[ADDIW]], 7
+  ; CHECK-NEXT:   [[FCVT_W_S:%[0-9]+]]:gpr = nofpexcept FCVT_W_S [[FCVT_S_W]], 1
+  ; CHECK-NEXT:   PseudoBR %bb.1
+  bb.1:
+    %7:gprb(s64) = G_CONSTANT i64 0
+    %3:gprb(s32) = G_TRUNC %7(s64)
+
+  bb.2:
+    %0:gprb(s32) = G_PHI %3(s32), %bb.1, %2(s32), %bb.2
+    %6:gprb(s64) = G_SEXT %0(s32)
+    %1:fprb(s32) = G_SITOFP %6(s64)
+    %5:gprb(s64) = G_FCVT_W_RV64 %1(s32), 1
+    %2:gprb(s32) = G_TRUNC %5(s64)
+    G_BR %bb.2
+
+...