Extract min<->max conversion into its own helper function

Author: mshockwave

llvm/include/llvm/CodeGen/ISDOpcodes.h

@@ -1506,6 +1506,8 @@ inline bool isBitwiseLogicOp(unsigned Opcode) {
   return Opcode == ISD::AND || Opcode == ISD::OR || Opcode == ISD::XOR;
 }
 
+NodeType getInverseMinMaxOpcode(unsigned MinMaxOpc);
+
 /// Get underlying scalar opcode for VECREDUCE opcode.
 /// For example ISD::AND for ISD::VECREDUCE_AND.
 NodeType getVecReduceBaseOpcode(unsigned VecReduceOpcode);

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

@@ -3962,23 +3962,7 @@ SDValue DAGCombiner::visitSUB(SDNode *N) {
                                       m_UMax(m_Value(X), NegPat),
                                       m_SMin(m_Value(X), NegPat),
                                       m_UMin(m_Value(X), NegPat))))) {
-      unsigned NewOpc = 0;
-      switch (N1->getOpcode()) {
-      case ISD::SMAX:
-        NewOpc = ISD::SMIN;
-        break;
-      case ISD::UMAX:
-        NewOpc = ISD::UMIN;
-        break;
-      case ISD::SMIN:
-        NewOpc = ISD::SMAX;
-        break;
-      case ISD::UMIN:
-        NewOpc = ISD::UMAX;
-        break;
-      default:
-        llvm_unreachable("unrecognized opcode");
-      }
+      unsigned NewOpc = ISD::getInverseMinMaxOpcode(N1->getOpcode());
       if (hasOperation(NewOpc, VT))
         return DAG.getNode(NewOpc, DL, VT, X, S0);
     }

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

@@ -430,6 +430,21 @@ bool ISD::matchBinaryPredicate(
   return true;
 }
 
+ISD::NodeType ISD::getInverseMinMaxOpcode(unsigned MinMaxOpc) {
+  switch (MinMaxOpc) {
+  default:
+    llvm_unreachable("unrecognized opcode");
+  case ISD::UMIN:
+    return ISD::UMAX;
+  case ISD::UMAX:
+    return ISD::UMIN;
+  case ISD::SMIN:
+    return ISD::SMAX;
+  case ISD::SMAX:
+    return ISD::SMIN;
+  }
+}
+
 ISD::NodeType ISD::getVecReduceBaseOpcode(unsigned VecReduceOpcode) {
   switch (VecReduceOpcode) {
   default: