[RISCV] add Double Trap extension requires Zicsr (#141016)

- The double trap extension requires `mtval2' register, so add Zicsr as
required extension

Signed-off-by: Jerry Zhang Jian <[email protected]>

Author: jerryzj

llvm/lib/Target/RISCV/RISCVFeatures.td

@@ -922,9 +922,9 @@ def FeatureStdExtSscsrind
     : RISCVExtension<1, 0, "Indirect CSR Access Supervisor Level">;
 
 def FeatureStdExtSmdbltrp
-    : RISCVExtension<1, 0, "Double Trap Machine Level">;
+    : RISCVExtension<1, 0, "Double Trap Machine Level", [FeatureStdExtZicsr]>;
 def FeatureStdExtSsdbltrp
-    : RISCVExtension<1, 0, "Double Trap Supervisor Level">;
+    : RISCVExtension<1, 0, "Double Trap Supervisor Level", [FeatureStdExtZicsr]>;
 
 def FeatureStdExtSmepmp
     : RISCVExtension<1, 0, "Enhanced Physical Memory Protection">;

llvm/test/CodeGen/RISCV/attributes.ll

@@ -496,8 +496,8 @@
 ; RV32SSAIA: .attribute 5, "rv32i2p1_ssaia1p0"
 ; RV32SMCSRIND: .attribute 5, "rv32i2p1_smcsrind1p0"
 ; RV32SSCSRIND: .attribute 5, "rv32i2p1_sscsrind1p0"
-; RV32SMDBLTRP: .attribute 5, "rv32i2p1_smdbltrp1p0"
-; RV32SSDBLTRP: .attribute 5, "rv32i2p1_ssdbltrp1p0"
+; RV32SMDBLTRP: .attribute 5, "rv32i2p1_zicsr2p0_smdbltrp1p0"
+; RV32SSDBLTRP: .attribute 5, "rv32i2p1_zicsr2p0_ssdbltrp1p0"
 ; RV32SSQOSID: .attribute 5, "rv32i2p1_ssqosid1p0"
 ; RV32SMCDELEG: .attribute 5, "rv32i2p1_smcdeleg1p0"
 ; RV32SMCNTRPMF: .attribute 5, "rv32i2p1_smcntrpmf1p0"
@@ -653,8 +653,8 @@
 ; RV64SSAIA: .attribute 5, "rv64i2p1_ssaia1p0"
 ; RV64SMCSRIND: .attribute 5, "rv64i2p1_smcsrind1p0"
 ; RV64SSCSRIND: .attribute 5, "rv64i2p1_sscsrind1p0"
-; RV64SMDBLTRP: .attribute 5, "rv64i2p1_smdbltrp1p0"
-; RV64SSDBLTRP: .attribute 5, "rv64i2p1_ssdbltrp1p0"
+; RV64SMDBLTRP: .attribute 5, "rv64i2p1_zicsr2p0_smdbltrp1p0"
+; RV64SSDBLTRP: .attribute 5, "rv64i2p1_zicsr2p0_ssdbltrp1p0"
 ; RV64SSQOSID: .attribute 5, "rv64i2p1_ssqosid1p0"
 ; RV64SMCDELEG: .attribute 5, "rv64i2p1_smcdeleg1p0"
 ; RV64SMCNTRPMF: .attribute 5, "rv64i2p1_smcntrpmf1p0"

llvm/test/MC/RISCV/attribute-arch.s

@@ -331,10 +331,10 @@
 # CHECK: attribute      5, "rv32i2p1_sscsrind1p0"
 
 .attribute arch, "rv32i_smdbltrp1p0"
-# CHECK: attribute      5, "rv32i2p1_smdbltrp1p0"
+# CHECK: attribute      5, "rv32i2p1_zicsr2p0_smdbltrp1p0"
 
 .attribute arch, "rv32i_ssdbltrp1p0"
-# CHECK: attribute      5, "rv32i2p1_ssdbltrp1p0"
+# CHECK: attribute      5, "rv32i2p1_zicsr2p0_ssdbltrp1p0"
 
 .attribute arch, "rv32i_smcdeleg1p0"
 # CHECK: attribute      5, "rv32i2p1_smcdeleg1p0"