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[𝘀𝗽𝗿] changes to main this commit is based on
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‎llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -297,6 +297,10 @@ class LegalizerHelper {
297297
MachineInstrBuilder createStackTemporary(TypeSize Bytes, Align Alignment,
298298
MachinePointerInfo &PtrInfo);
299299

300+
/// Create a store of \p Val to a stack temporary and return a load of the
301+
/// same value as type \p DestVT.
302+
MachineInstrBuilder createStackStoreLoad(Register Val, LLT DstTy);
303+
300304
/// Get a pointer to vector element \p Index located in memory for a vector of
301305
/// type \p VecTy starting at a base address of \p VecPtr. If \p Index is out
302306
/// of bounds the returned pointer is unspecified, but will be within the

‎llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp‎

Lines changed: 60 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,7 @@
2222
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
2323
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
2424
#include "llvm/CodeGen/GlobalISel/Utils.h"
25+
#include "llvm/CodeGen/LowLevelTypeUtils.h"
2526
#include "llvm/CodeGen/MachineConstantPool.h"
2627
#include "llvm/CodeGen/MachineFrameInfo.h"
2728
#include "llvm/CodeGen/MachineRegisterInfo.h"
@@ -3022,8 +3023,18 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
30223023
return UnableToLegalize;
30233024

30243025
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
3025-
if (!Ty.isScalar())
3026-
return UnableToLegalize;
3026+
if (!Ty.isScalar()) {
3027+
// We need to widen the vector element type.
3028+
Observer.changingInstr(MI);
3029+
widenScalarSrc(MI, WideTy, 0, TargetOpcode::G_ANYEXT);
3030+
// We also need to adjust the MMO to turn this into a truncating store.
3031+
MachineMemOperand &MMO = **MI.memoperands_begin();
3032+
MachineFunction &MF = MIRBuilder.getMF();
3033+
auto *NewMMO = MF.getMachineMemOperand(&MMO, MMO.getPointerInfo(), Ty);
3034+
MI.setMemRefs(MF, {NewMMO});
3035+
Observer.changedInstr(MI);
3036+
return Legalized;
3037+
}
30273038

30283039
Observer.changingInstr(MI);
30293040

@@ -4131,9 +4142,40 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerStore(GStore &StoreMI) {
41314142
}
41324143

41334144
if (MemTy.isVector()) {
4134-
// TODO: Handle vector trunc stores
4135-
if (MemTy != SrcTy)
4145+
LLT MemScalarTy = MemTy.getElementType();
4146+
if (MemTy != SrcTy) {
4147+
if (!MemScalarTy.isByteSized()) {
4148+
// We need to build an integer scalar of the vector bit pattern.
4149+
// It's not legal for us to add padding when storing a vector.
4150+
unsigned NumBits = MemTy.getSizeInBits();
4151+
LLT IntTy = LLT::scalar(NumBits);
4152+
auto CurrVal = MIRBuilder.buildConstant(IntTy, 0);
4153+
LLT IdxTy = getLLTForMVT(TLI.getVectorIdxTy(MF.getDataLayout()));
4154+
4155+
for (unsigned I = 0, E = MemTy.getNumElements(); I < E; ++I) {
4156+
auto Elt = MIRBuilder.buildExtractVectorElement(
4157+
SrcTy.getElementType(), SrcReg,
4158+
MIRBuilder.buildConstant(IdxTy, I));
4159+
auto Trunc = MIRBuilder.buildTrunc(MemScalarTy, Elt);
4160+
auto ZExt = MIRBuilder.buildZExt(IntTy, Trunc);
4161+
unsigned ShiftIntoIdx = MF.getDataLayout().isBigEndian()
4162+
? (MemTy.getNumElements() - 1) - I
4163+
: I;
4164+
auto ShiftAmt = MIRBuilder.buildConstant(
4165+
IntTy, ShiftIntoIdx * MemScalarTy.getSizeInBits());
4166+
auto Shifted = MIRBuilder.buildShl(IntTy, ZExt, ShiftAmt);
4167+
CurrVal = MIRBuilder.buildOr(IntTy, CurrVal, Shifted);
4168+
}
4169+
auto PtrInfo = MMO.getPointerInfo();
4170+
auto *NewMMO = MF.getMachineMemOperand(&MMO, PtrInfo, IntTy);
4171+
MIRBuilder.buildStore(CurrVal, PtrReg, *NewMMO);
4172+
StoreMI.eraseFromParent();
4173+
return Legalized;
4174+
}
4175+
4176+
// FIXME: implement simple scalarization.
41364177
return UnableToLegalize;
4178+
}
41374179

41384180
// TODO: We can do better than scalarizing the vector and at least split it
41394181
// in half.
@@ -4653,6 +4695,20 @@ LegalizerHelper::createStackTemporary(TypeSize Bytes, Align Alignment,
46534695
return MIRBuilder.buildFrameIndex(FramePtrTy, FrameIdx);
46544696
}
46554697

4698+
MachineInstrBuilder LegalizerHelper::createStackStoreLoad(Register Val,
4699+
LLT DstTy) {
4700+
LLT SrcTy = MRI.getType(Val);
4701+
Align StackTypeAlign = getStackTemporaryAlignment(SrcTy);
4702+
MachinePointerInfo PtrInfo;
4703+
auto StackTemp =
4704+
createStackTemporary(SrcTy.getSizeInBytes(), StackTypeAlign, PtrInfo);
4705+
4706+
MIRBuilder.buildStore(Val, StackTemp, PtrInfo, StackTypeAlign);
4707+
return MIRBuilder.buildLoad(
4708+
DstTy, StackTemp, PtrInfo,
4709+
std::min(StackTypeAlign, getStackTemporaryAlignment(DstTy)));
4710+
}
4711+
46564712
static Register clampVectorIndex(MachineIRBuilder &B, Register IdxReg,
46574713
LLT VecTy) {
46584714
LLT IdxTy = B.getMRI()->getType(IdxReg);

‎llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp‎

Lines changed: 28 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -454,6 +454,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
454454
{nxv2s64, p0, nxv2s64, 8},
455455
})
456456
.clampScalar(0, s8, s64)
457+
.minScalarOrElt(0, s8)
457458
.lowerIf([=](const LegalityQuery &Query) {
458459
return Query.Types[0].isScalar() &&
459460
Query.Types[0] != Query.MMODescrs[0].MemoryTy;
@@ -473,7 +474,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
473474
})
474475
.customIf(IsPtrVecPred)
475476
.scalarizeIf(typeInSet(0, {v2s16, v2s8}), 0)
476-
.scalarizeIf(scalarOrEltWiderThan(0, 64), 0);
477+
.scalarizeIf(scalarOrEltWiderThan(0, 64), 0)
478+
.lower();
477479

478480
getActionDefinitionsBuilder(G_INDEXED_STORE)
479481
// Idx 0 == Ptr, Idx 1 == Val
@@ -861,6 +863,13 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
861863
.legalForCartesianProduct({s32, v2s16, v4s8})
862864
.legalForCartesianProduct({s64, v8s8, v4s16, v2s32})
863865
.legalForCartesianProduct({s128, v16s8, v8s16, v4s32, v2s64, v2p0})
866+
.customIf([=](const LegalityQuery &Query) {
867+
// Handle casts from i1 vectors to scalars.
868+
LLT DstTy = Query.Types[0];
869+
LLT SrcTy = Query.Types[1];
870+
return DstTy.isScalar() && SrcTy.isVector() &&
871+
SrcTy.getScalarSizeInBits() == 1;
872+
})
864873
.lowerIf([=](const LegalityQuery &Query) {
865874
return Query.Types[0].isVector() != Query.Types[1].isVector();
866875
})
@@ -1404,11 +1413,29 @@ bool AArch64LegalizerInfo::legalizeCustom(
14041413
return Helper.lowerAbsToCNeg(MI);
14051414
case TargetOpcode::G_ICMP:
14061415
return legalizeICMP(MI, MRI, MIRBuilder);
1416+
case TargetOpcode::G_BITCAST:
1417+
return legalizeBitcast(MI, Helper);
14071418
}
14081419

14091420
llvm_unreachable("expected switch to return");
14101421
}
14111422

1423+
bool AArch64LegalizerInfo::legalizeBitcast(MachineInstr &MI,
1424+
LegalizerHelper &Helper) const {
1425+
assert(MI.getOpcode() == TargetOpcode::G_BITCAST && "Unexpected opcode");
1426+
auto [DstReg, DstTy, SrcReg, SrcTy] = MI.getFirst2RegLLTs();
1427+
// We're trying to handle casts from i1 vectors to scalars but reloading from
1428+
// stack.
1429+
if (!DstTy.isScalar() || !SrcTy.isVector() ||
1430+
SrcTy.getElementType() != LLT::scalar(1))
1431+
return false;
1432+
1433+
auto Load = Helper.createStackStoreLoad(SrcReg, DstTy);
1434+
Helper.MIRBuilder.buildCopy(DstReg, Load.getReg(0));
1435+
MI.eraseFromParent();
1436+
return true;
1437+
}
1438+
14121439
bool AArch64LegalizerInfo::legalizeFunnelShift(MachineInstr &MI,
14131440
MachineRegisterInfo &MRI,
14141441
MachineIRBuilder &MIRBuilder,

‎llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -66,6 +66,7 @@ class AArch64LegalizerInfo : public LegalizerInfo {
6666
LegalizerHelper &Helper) const;
6767
bool legalizeDynStackAlloc(MachineInstr &MI, LegalizerHelper &Helper) const;
6868
bool legalizePrefetch(MachineInstr &MI, LegalizerHelper &Helper) const;
69+
bool legalizeBitcast(MachineInstr &MI, LegalizerHelper &Helper) const;
6970
const AArch64Subtarget *ST;
7071
};
7172
} // End llvm namespace.

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-bitcast.mir‎

Lines changed: 71 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -48,3 +48,74 @@ body: |
4848
G_BR %bb.2
4949
5050
...
51+
---
52+
name: boolean_vector_to_scalar
53+
tracksRegLiveness: true
54+
body: |
55+
bb.1:
56+
; CHECK-LABEL: name: boolean_vector_to_scalar
57+
; CHECK: [[DEF:%[0-9]+]]:_(<8 x s8>) = G_IMPLICIT_DEF
58+
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
59+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
60+
; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x s8>), [[C]](s64)
61+
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC]](s8)
62+
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
63+
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C1]]
64+
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s64)
65+
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
66+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[C2]], [[SHL]]
67+
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
68+
; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x s8>), [[C3]](s64)
69+
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC1]](s8)
70+
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C1]]
71+
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C3]](s64)
72+
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
73+
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
74+
; CHECK-NEXT: [[EVEC2:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x s8>), [[C4]](s64)
75+
; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC2]](s8)
76+
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C1]]
77+
; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C4]](s64)
78+
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
79+
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
80+
; CHECK-NEXT: [[EVEC3:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x s8>), [[C5]](s64)
81+
; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC3]](s8)
82+
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ANYEXT3]], [[C1]]
83+
; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C5]](s64)
84+
; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[SHL3]]
85+
; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
86+
; CHECK-NEXT: [[EVEC4:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x s8>), [[C6]](s64)
87+
; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC4]](s8)
88+
; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ANYEXT4]], [[C1]]
89+
; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C6]](s64)
90+
; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
91+
; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
92+
; CHECK-NEXT: [[EVEC5:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x s8>), [[C7]](s64)
93+
; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC5]](s8)
94+
; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ANYEXT5]], [[C1]]
95+
; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C7]](s64)
96+
; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
97+
; CHECK-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
98+
; CHECK-NEXT: [[EVEC6:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x s8>), [[C8]](s64)
99+
; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC6]](s8)
100+
; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ANYEXT6]], [[C1]]
101+
; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C8]](s64)
102+
; CHECK-NEXT: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR5]], [[SHL6]]
103+
; CHECK-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
104+
; CHECK-NEXT: [[EVEC7:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x s8>), [[C9]](s64)
105+
; CHECK-NEXT: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC7]](s8)
106+
; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ANYEXT7]], [[C1]]
107+
; CHECK-NEXT: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C9]](s64)
108+
; CHECK-NEXT: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
109+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[OR7]](s32)
110+
; CHECK-NEXT: G_STORE [[TRUNC]](s8), [[FRAME_INDEX]](p0) :: (store (s8) into %stack.0)
111+
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s8) from %stack.0)
112+
; CHECK-NEXT: %bc:_(s8) = COPY [[LOAD]](s8)
113+
; CHECK-NEXT: %ext:_(s32) = G_ANYEXT %bc(s8)
114+
; CHECK-NEXT: $w0 = COPY %ext(s32)
115+
; CHECK-NEXT: RET_ReallyLR implicit $w0
116+
%vec:_(<8 x s1>) = G_IMPLICIT_DEF
117+
%bc:_(s8) = G_BITCAST %vec(<8 x s1>)
118+
%ext:_(s32) = G_ANYEXT %bc(s8)
119+
$w0 = COPY %ext(s32)
120+
RET_ReallyLR implicit $w0
121+
...

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-store-vector-bools.mir‎

Lines changed: 86 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,86 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
2+
# RUN: llc -O0 -mtriple=aarch64 -run-pass=legalizer -global-isel-abort=1 %s -o - | FileCheck %s
3+
---
4+
name: store_8xs1
5+
tracksRegLiveness: true
6+
body: |
7+
bb.1:
8+
liveins: $q0, $q1, $x0
9+
; CHECK-LABEL: name: store_8xs1
10+
; CHECK: liveins: $q0, $q1, $x0
11+
; CHECK-NEXT: {{ $}}
12+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
13+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
14+
; CHECK-NEXT: %ptr:_(p0) = COPY $x0
15+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
16+
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
17+
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
18+
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(slt), [[COPY]](<4 x s32>), [[BUILD_VECTOR]]
19+
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(slt), [[COPY1]](<4 x s32>), [[BUILD_VECTOR1]]
20+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>)
21+
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP1]](<4 x s32>)
22+
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[TRUNC]](<4 x s16>), [[TRUNC1]](<4 x s16>)
23+
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[CONCAT_VECTORS]](<8 x s16>)
24+
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
25+
; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C1]](s64)
26+
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC]](s8)
27+
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
28+
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C2]]
29+
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C1]](s64)
30+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
31+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[SHL]]
32+
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
33+
; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C3]](s64)
34+
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC1]](s8)
35+
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C2]]
36+
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C3]](s64)
37+
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
38+
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
39+
; CHECK-NEXT: [[EVEC2:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C4]](s64)
40+
; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC2]](s8)
41+
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C2]]
42+
; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C4]](s64)
43+
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
44+
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
45+
; CHECK-NEXT: [[EVEC3:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C5]](s64)
46+
; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC3]](s8)
47+
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ANYEXT3]], [[C2]]
48+
; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C5]](s64)
49+
; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[SHL3]]
50+
; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
51+
; CHECK-NEXT: [[EVEC4:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C6]](s64)
52+
; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC4]](s8)
53+
; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ANYEXT4]], [[C2]]
54+
; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C6]](s64)
55+
; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
56+
; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
57+
; CHECK-NEXT: [[EVEC5:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C7]](s64)
58+
; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC5]](s8)
59+
; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ANYEXT5]], [[C2]]
60+
; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C7]](s64)
61+
; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
62+
; CHECK-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
63+
; CHECK-NEXT: [[EVEC6:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C8]](s64)
64+
; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC6]](s8)
65+
; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ANYEXT6]], [[C2]]
66+
; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C8]](s64)
67+
; CHECK-NEXT: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR5]], [[SHL6]]
68+
; CHECK-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
69+
; CHECK-NEXT: [[EVEC7:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C9]](s64)
70+
; CHECK-NEXT: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC7]](s8)
71+
; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ANYEXT7]], [[C2]]
72+
; CHECK-NEXT: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C9]](s64)
73+
; CHECK-NEXT: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
74+
; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[OR7]](s32)
75+
; CHECK-NEXT: G_STORE [[TRUNC3]](s8), %ptr(p0) :: (store (s8))
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; CHECK-NEXT: RET_ReallyLR
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%1:_(<4 x s32>) = COPY $q0
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%2:_(<4 x s32>) = COPY $q1
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%ptr:_(p0) = COPY $x0
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%0:_(<8 x s32>) = G_CONCAT_VECTORS %1(<4 x s32>), %2(<4 x s32>)
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%4:_(s32) = G_CONSTANT i32 0
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%3:_(<8 x s32>) = G_BUILD_VECTOR %4(s32), %4(s32), %4(s32), %4(s32), %4(s32), %4(s32), %4(s32), %4(s32)
83+
%5:_(<8 x s1>) = G_ICMP intpred(slt), %0(<8 x s32>), %3
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G_STORE %5(<8 x s1>), %ptr(p0) :: (store (<8 x s1>))
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RET_ReallyLR
86+
...

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