[X86] Use Register and MCRegister. NFC

Author: topperc

llvm/lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp

@@ -533,7 +533,7 @@ void X86AvoidSFBPass::findPotentiallylBlockedCopies(MachineFunction &MF) {
     for (auto &MI : MBB) {
       if (!isPotentialBlockedMemCpyLd(MI.getOpcode()))
         continue;
-      int DefVR = MI.getOperand(0).getReg();
+      Register DefVR = MI.getOperand(0).getReg();
       if (!MRI->hasOneNonDBGUse(DefVR))
         continue;
       for (MachineOperand &StoreMO :

llvm/lib/Target/X86/X86CallFrameOptimization.cpp

@@ -112,7 +112,7 @@ class X86CallFrameOptimization : public MachineFunctionPass {
   InstClassification classifyInstruction(MachineBasicBlock &MBB,
                                          MachineBasicBlock::iterator MI,
                                          const X86RegisterInfo &RegInfo,
-                                         DenseSet<unsigned int> &UsedRegs);
+                                         const DenseSet<MCRegister> &UsedRegs);
 
   StringRef getPassName() const override { return "X86 Optimize Call Frame"; }
 
@@ -278,7 +278,7 @@ bool X86CallFrameOptimization::runOnMachineFunction(MachineFunction &MF) {
 X86CallFrameOptimization::InstClassification
 X86CallFrameOptimization::classifyInstruction(
     MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
-    const X86RegisterInfo &RegInfo, DenseSet<unsigned int> &UsedRegs) {
+    const X86RegisterInfo &RegInfo, const DenseSet<MCRegister> &UsedRegs) {
   if (MI == MBB.end())
     return Exit;
 
@@ -341,7 +341,7 @@ X86CallFrameOptimization::classifyInstruction(
     if (RegInfo.regsOverlap(Reg, RegInfo.getStackRegister()))
       return Exit;
     if (MO.isDef()) {
-      for (unsigned int U : UsedRegs)
+      for (MCRegister U : UsedRegs)
         if (RegInfo.regsOverlap(Reg, U))
           return Exit;
     }
@@ -406,7 +406,7 @@ void X86CallFrameOptimization::collectCallInfo(MachineFunction &MF,
   if (MaxAdjust > 4)
     Context.ArgStoreVector.resize(MaxAdjust, nullptr);
 
-  DenseSet<unsigned int> UsedRegs;
+  DenseSet<MCRegister> UsedRegs;
 
   for (InstClassification Classification = Skip; Classification != Exit; ++I) {
     // If this is the COPY of the stack pointer, it's ok to ignore.
@@ -455,7 +455,7 @@ void X86CallFrameOptimization::collectCallInfo(MachineFunction &MF,
         continue;
       Register Reg = MO.getReg();
       if (Reg.isPhysical())
-        UsedRegs.insert(Reg);
+        UsedRegs.insert(Reg.asMCReg());
     }
   }
 

llvm/lib/Target/X86/X86CmovConversion.cpp

@@ -406,7 +406,7 @@ bool X86CmovConverterPass::checkForProfitableCmovCandidates(
   DepthInfo LoopDepth[LoopIterations] = {{0, 0}, {0, 0}};
   enum { PhyRegType = 0, VirRegType = 1, RegTypeNum = 2 };
   /// For each register type maps the register to its last def instruction.
-  DenseMap<unsigned, MachineInstr *> RegDefMaps[RegTypeNum];
+  DenseMap<Register, MachineInstr *> RegDefMaps[RegTypeNum];
   /// Maps register operand to its def instruction, which can be nullptr if it
   /// is unknown (e.g., operand is defined outside the loop).
   DenseMap<MachineOperand *, MachineInstr *> OperandToDefMap;
@@ -723,7 +723,7 @@ void X86CmovConverterPass::convertCmovInstsToBranches(
   // operand. We also need to potentially do register rewriting here, but it is
   // simpler as the memory operands are always on the false path so we can
   // simply take that input, whatever it is.
-  DenseMap<unsigned, unsigned> FalseBBRegRewriteTable;
+  DenseMap<Register, Register> FalseBBRegRewriteTable;
   for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd;) {
     auto &MI = *MIIt++;
     // Skip any CMOVs in this group which don't load from memory.
@@ -830,7 +830,7 @@ void X86CmovConverterPass::convertCmovInstsToBranches(
   // That also means that PHI construction must work forward from earlier to
   // later, and that the code must maintain a mapping from earlier PHI's
   // destination registers, and the registers that went into the PHI.
-  DenseMap<unsigned, std::pair<unsigned, unsigned>> RegRewriteTable;
+  DenseMap<Register, std::pair<Register, Register>> RegRewriteTable;
 
   for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; ++MIIt) {
     Register DestReg = MIIt->getOperand(0).getReg();

llvm/lib/Target/X86/X86CompressEVEX.cpp

@@ -83,7 +83,7 @@ class CompressEVEXPass : public MachineFunctionPass {
 char CompressEVEXPass::ID = 0;
 
 static bool usesExtendedRegister(const MachineInstr &MI) {
-  auto isHiRegIdx = [](unsigned Reg) {
+  auto isHiRegIdx = [](MCRegister Reg) {
     // Check for XMM register with indexes between 16 - 31.
     if (Reg >= X86::XMM16 && Reg <= X86::XMM31)
       return true;
@@ -102,7 +102,7 @@ static bool usesExtendedRegister(const MachineInstr &MI) {
     if (!MO.isReg())
       continue;
 
-    Register Reg = MO.getReg();
+    MCRegister Reg = MO.getReg().asMCReg();
     assert(!X86II::isZMMReg(Reg) &&
            "ZMM instructions should not be in the EVEX->VEX tables");
     if (isHiRegIdx(Reg))

llvm/lib/Target/X86/X86DomainReassignment.cpp

@@ -400,7 +400,7 @@ class X86DomainReassignment : public MachineFunctionPass {
   /// Enqueue \p Reg to be considered for addition to the closure.
   /// Return false if the closure becomes invalid.
   bool visitRegister(Closure &, Register Reg, RegDomain &Domain,
-                     SmallVectorImpl<unsigned> &Worklist);
+                     SmallVectorImpl<Register> &Worklist);
 
   /// Reassign the closure to \p Domain.
   void reassign(const Closure &C, RegDomain Domain) const;
@@ -422,7 +422,7 @@ char X86DomainReassignment::ID = 0;
 
 bool X86DomainReassignment::visitRegister(Closure &C, Register Reg,
                                           RegDomain &Domain,
-                                          SmallVectorImpl<unsigned> &Worklist) {
+                                          SmallVectorImpl<Register> &Worklist) {
   if (!Reg.isVirtual())
     return true;
 
@@ -544,11 +544,11 @@ static bool usedAsAddr(const MachineInstr &MI, Register Reg,
 }
 
 void X86DomainReassignment::buildClosure(Closure &C, Register Reg) {
-  SmallVector<unsigned, 4> Worklist;
+  SmallVector<Register, 4> Worklist;
   RegDomain Domain = NoDomain;
   visitRegister(C, Reg, Domain, Worklist);
   while (!Worklist.empty()) {
-    unsigned CurReg = Worklist.pop_back_val();
+    Register CurReg = Worklist.pop_back_val();
 
     // Register already in this closure.
     if (!C.insertEdge(CurReg))

llvm/lib/Target/X86/X86DynAllocaExpander.cpp

@@ -57,7 +57,7 @@ class X86DynAllocaExpander : public MachineFunctionPass {
   const X86Subtarget *STI = nullptr;
   const TargetInstrInfo *TII = nullptr;
   const X86RegisterInfo *TRI = nullptr;
-  unsigned StackPtr = 0;
+  Register StackPtr;
   unsigned SlotSize = 0;
   int64_t StackProbeSize = 0;
   bool NoStackArgProbe = false;

llvm/lib/Target/X86/X86FastISel.cpp

@@ -2684,7 +2684,7 @@ bool X86FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
     MFI.setFrameAddressIsTaken(true);
 
     const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
-    unsigned FrameReg = RegInfo->getPtrSizedFrameRegister(*MF);
+    Register FrameReg = RegInfo->getPtrSizedFrameRegister(*MF);
     assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
             (FrameReg == X86::EBP && VT == MVT::i32)) &&
            "Invalid Frame Register!");
@@ -3478,7 +3478,7 @@ bool X86FastISel::fastLowerCall(CallLoweringInfo &CLI) {
   // ELF / PIC requires GOT in the EBX register before function calls via PLT
   // GOT pointer.
   if (Subtarget->isPICStyleGOT()) {
-    unsigned Base = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
+    Register Base = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
             TII.get(TargetOpcode::COPY), X86::EBX).addReg(Base);
   }
@@ -3510,11 +3510,11 @@ bool X86FastISel::fastLowerCall(CallLoweringInfo &CLI) {
   if (!X86SelectCallAddress(Callee, CalleeAM))
     return false;
 
-  unsigned CalleeOp = 0;
+  Register CalleeOp;
   const GlobalValue *GV = nullptr;
   if (CalleeAM.GV != nullptr) {
     GV = CalleeAM.GV;
-  } else if (CalleeAM.Base.Reg != 0) {
+  } else if (CalleeAM.Base.Reg) {
     CalleeOp = CalleeAM.Base.Reg;
   } else
     return false;
@@ -3816,7 +3816,7 @@ Register X86FastISel::X86MaterializeFP(const ConstantFP *CFP, MVT VT) {
   Align Alignment = DL.getPrefTypeAlign(CFP->getType());
 
   // x86-32 PIC requires a PIC base register for constant pools.
-  unsigned PICBase = 0;
+  Register PICBase;
   unsigned char OpFlag = Subtarget->classifyLocalReference(nullptr);
   if (OpFlag == X86II::MO_PIC_BASE_OFFSET)
     PICBase = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);

llvm/lib/Target/X86/X86FixupLEAs.cpp

@@ -325,7 +325,7 @@ FixupLEAPass::searchBackwards(MachineOperand &p, MachineBasicBlock::iterator &I,
   return MachineBasicBlock::iterator();
 }
 
-static inline bool isInefficientLEAReg(unsigned Reg) {
+static inline bool isInefficientLEAReg(Register Reg) {
   return Reg == X86::EBP || Reg == X86::RBP ||
          Reg == X86::R13D || Reg == X86::R13;
 }
@@ -337,7 +337,7 @@ static inline bool isInefficientLEAReg(unsigned Reg) {
 static inline bool hasInefficientLEABaseReg(const MachineOperand &Base,
                                             const MachineOperand &Index) {
   return Base.isReg() && isInefficientLEAReg(Base.getReg()) && Index.isReg() &&
-         Index.getReg() != X86::NoRegister;
+         Index.getReg().isValid();
 }
 
 static inline bool hasLEAOffset(const MachineOperand &Offset) {
@@ -557,7 +557,7 @@ bool FixupLEAPass::optTwoAddrLEA(MachineBasicBlock::iterator &I,
   const MachineOperand &Disp =    MI.getOperand(1 + X86::AddrDisp);
   const MachineOperand &Segment = MI.getOperand(1 + X86::AddrSegmentReg);
 
-  if (Segment.getReg() != 0 || !Disp.isImm() || Scale.getImm() > 1 ||
+  if (Segment.getReg().isValid() || !Disp.isImm() || Scale.getImm() > 1 ||
       MBB.computeRegisterLiveness(TRI, X86::EFLAGS, I) !=
           MachineBasicBlock::LQR_Dead)
     return false;
@@ -572,9 +572,9 @@ bool FixupLEAPass::optTwoAddrLEA(MachineBasicBlock::iterator &I,
 
   // LEA64_32 has 64-bit operands but 32-bit result.
   if (MI.getOpcode() == X86::LEA64_32r) {
-    if (BaseReg != 0)
+    if (BaseReg)
       BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit);
-    if (IndexReg != 0)
+    if (IndexReg)
       IndexReg = TRI->getSubReg(IndexReg, X86::sub_32bit);
   }
 
@@ -583,7 +583,7 @@ bool FixupLEAPass::optTwoAddrLEA(MachineBasicBlock::iterator &I,
   // Case 1.
   // Look for lea(%reg1, %reg2), %reg1 or lea(%reg2, %reg1), %reg1
   // which can be turned into add %reg2, %reg1
-  if (BaseReg != 0 && IndexReg != 0 && Disp.getImm() == 0 &&
+  if (BaseReg.isValid() && IndexReg.isValid() && Disp.getImm() == 0 &&
       (DestReg == BaseReg || DestReg == IndexReg)) {
     unsigned NewOpcode = getADDrrFromLEA(MI.getOpcode());
     if (DestReg != BaseReg)
@@ -599,7 +599,7 @@ bool FixupLEAPass::optTwoAddrLEA(MachineBasicBlock::iterator &I,
       NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
         .addReg(BaseReg).addReg(IndexReg);
     }
-  } else if (DestReg == BaseReg && IndexReg == 0) {
+  } else if (DestReg == BaseReg && !IndexReg) {
     // Case 2.
     // This is an LEA with only a base register and a displacement,
     // We can use ADDri or INC/DEC.
@@ -631,7 +631,7 @@ bool FixupLEAPass::optTwoAddrLEA(MachineBasicBlock::iterator &I,
           .addReg(BaseReg).addImm(Disp.getImm());
       }
     }
-  } else if (BaseReg != 0 && IndexReg != 0 && Disp.getImm() == 0) {
+  } else if (BaseReg.isValid() && IndexReg.isValid() && Disp.getImm() == 0) {
     // Case 3.
     // Look for and transform the sequence
     //     lea (reg1, reg2), reg3
@@ -697,22 +697,22 @@ void FixupLEAPass::processInstructionForSlowLEA(MachineBasicBlock::iterator &I,
   const MachineOperand &Offset =  MI.getOperand(1 + X86::AddrDisp);
   const MachineOperand &Segment = MI.getOperand(1 + X86::AddrSegmentReg);
 
-  if (Segment.getReg() != 0 || !Offset.isImm() ||
+  if (Segment.getReg().isValid() || !Offset.isImm() ||
       MBB.computeRegisterLiveness(TRI, X86::EFLAGS, I, 4) !=
           MachineBasicBlock::LQR_Dead)
     return;
   const Register DstR = Dst.getReg();
   const Register SrcR1 = Base.getReg();
   const Register SrcR2 = Index.getReg();
-  if ((SrcR1 == 0 || SrcR1 != DstR) && (SrcR2 == 0 || SrcR2 != DstR))
+  if ((!SrcR1 || SrcR1 != DstR) && (!SrcR2 || SrcR2 != DstR))
     return;
   if (Scale.getImm() > 1)
     return;
   LLVM_DEBUG(dbgs() << "FixLEA: Candidate to replace:"; I->dump(););
   LLVM_DEBUG(dbgs() << "FixLEA: Replaced by: ";);
   MachineInstr *NewMI = nullptr;
   // Make ADD instruction for two registers writing to LEA's destination
-  if (SrcR1 != 0 && SrcR2 != 0) {
+  if (SrcR1 && SrcR2) {
     const MCInstrDesc &ADDrr = TII->get(getADDrrFromLEA(Opcode));
     const MachineOperand &Src = SrcR1 == DstR ? Index : Base;
     NewMI =
@@ -752,17 +752,17 @@ void FixupLEAPass::processInstrForSlow3OpLEA(MachineBasicBlock::iterator &I,
   if (!(TII->isThreeOperandsLEA(MI) || hasInefficientLEABaseReg(Base, Index)) ||
       MBB.computeRegisterLiveness(TRI, X86::EFLAGS, I, 4) !=
           MachineBasicBlock::LQR_Dead ||
-      Segment.getReg() != X86::NoRegister)
+      Segment.getReg().isValid())
     return;
 
   Register DestReg = Dest.getReg();
   Register BaseReg = Base.getReg();
   Register IndexReg = Index.getReg();
 
   if (MI.getOpcode() == X86::LEA64_32r) {
-    if (BaseReg != 0)
+    if (BaseReg)
       BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit);
-    if (IndexReg != 0)
+    if (IndexReg)
       IndexReg = TRI->getSubReg(IndexReg, X86::sub_32bit);
   }
 

llvm/lib/Target/X86/X86FlagsCopyLowering.cpp

@@ -69,7 +69,7 @@ STATISTIC(NumNFsConvertedTo, "Number of NF instructions converted to");
 namespace {
 
 // Convenient array type for storing registers associated with each condition.
-using CondRegArray = std::array<unsigned, X86::LAST_VALID_COND + 1>;
+using CondRegArray = std::array<Register, X86::LAST_VALID_COND + 1>;
 
 class X86FlagsCopyLoweringPass : public MachineFunctionPass {
 public:
@@ -96,11 +96,11 @@ class X86FlagsCopyLoweringPass : public MachineFunctionPass {
   Register promoteCondToReg(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator TestPos,
                             const DebugLoc &TestLoc, X86::CondCode Cond);
-  std::pair<unsigned, bool> getCondOrInverseInReg(
+  std::pair<Register, bool> getCondOrInverseInReg(
       MachineBasicBlock &TestMBB, MachineBasicBlock::iterator TestPos,
       const DebugLoc &TestLoc, X86::CondCode Cond, CondRegArray &CondRegs);
   void insertTest(MachineBasicBlock &MBB, MachineBasicBlock::iterator Pos,
-                  const DebugLoc &Loc, unsigned Reg);
+                  const DebugLoc &Loc, Register Reg);
 
   void rewriteSetCC(MachineBasicBlock &MBB, MachineBasicBlock::iterator Pos,
                     const DebugLoc &Loc, MachineInstr &MI,
@@ -744,11 +744,11 @@ Register X86FlagsCopyLoweringPass::promoteCondToReg(
   return Reg;
 }
 
-std::pair<unsigned, bool> X86FlagsCopyLoweringPass::getCondOrInverseInReg(
+std::pair<Register, bool> X86FlagsCopyLoweringPass::getCondOrInverseInReg(
     MachineBasicBlock &TestMBB, MachineBasicBlock::iterator TestPos,
     const DebugLoc &TestLoc, X86::CondCode Cond, CondRegArray &CondRegs) {
-  unsigned &CondReg = CondRegs[Cond];
-  unsigned &InvCondReg = CondRegs[X86::GetOppositeBranchCondition(Cond)];
+  Register &CondReg = CondRegs[Cond];
+  Register &InvCondReg = CondRegs[X86::GetOppositeBranchCondition(Cond)];
   if (!CondReg && !InvCondReg)
     CondReg = promoteCondToReg(TestMBB, TestPos, TestLoc, Cond);
 
@@ -760,7 +760,7 @@ std::pair<unsigned, bool> X86FlagsCopyLoweringPass::getCondOrInverseInReg(
 
 void X86FlagsCopyLoweringPass::insertTest(MachineBasicBlock &MBB,
                                           MachineBasicBlock::iterator Pos,
-                                          const DebugLoc &Loc, unsigned Reg) {
+                                          const DebugLoc &Loc, Register Reg) {
   auto TestI =
       BuildMI(MBB, Pos, Loc, TII->get(X86::TEST8rr)).addReg(Reg).addReg(Reg);
   (void)TestI;
@@ -777,7 +777,7 @@ void X86FlagsCopyLoweringPass::rewriteSetCC(MachineBasicBlock &MBB,
   // Note that we can't usefully rewrite this to the inverse without complex
   // analysis of the users of the setCC. Largely we rely on duplicates which
   // could have been avoided already being avoided here.
-  unsigned &CondReg = CondRegs[Cond];
+  Register &CondReg = CondRegs[Cond];
   if (!CondReg)
     CondReg = promoteCondToReg(MBB, Pos, Loc, Cond);
 
@@ -843,7 +843,7 @@ void X86FlagsCopyLoweringPass::rewriteArithmetic(
   // Now get a register that contains the value of the flag input to the
   // arithmetic. We require exactly this flag to simplify the arithmetic
   // required to materialize it back into the flag.
-  unsigned &CondReg = CondRegs[Cond];
+  Register &CondReg = CondRegs[Cond];
   if (!CondReg)
     CondReg = promoteCondToReg(MBB, Pos, Loc, Cond);
 
@@ -917,7 +917,7 @@ void X86FlagsCopyLoweringPass::rewriteMI(MachineBasicBlock &MBB,
     IsImplicitCC = true;
   }
   assert(CC != X86::COND_INVALID && "Unknown EFLAG user!");
-  unsigned CondReg;
+  Register CondReg;
   bool Inverted;
   std::tie(CondReg, Inverted) =
       getCondOrInverseInReg(MBB, Pos, Loc, CC, CondRegs);

llvm/lib/Target/X86/X86FloatingPoint.cpp

@@ -462,7 +462,7 @@ bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
 
     // Get dead variables list now because the MI pointer may be deleted as part
     // of processing!
-    SmallVector<unsigned, 8> DeadRegs;
+    SmallVector<Register, 8> DeadRegs;
     for (const MachineOperand &MO : MI.operands())
       if (MO.isReg() && MO.isDead())
         DeadRegs.push_back(MO.getReg());
@@ -480,7 +480,7 @@ bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
 
     // Check to see if any of the values defined by this instruction are dead
     // after definition.  If so, pop them.
-    for (unsigned Reg : DeadRegs) {
+    for (Register Reg : DeadRegs) {
       // Check if Reg is live on the stack. An inline-asm register operand that
       // is in the clobber list and marked dead might not be live on the stack.
       static_assert(X86::FP7 - X86::FP0 == 7, "sequential FP regnumbers");