Skip to content

Commit 3ffe04f

Browse files
committed
fixup! Create its own decoder for VMV0 register class
1 parent a5af348 commit 3ffe04f

File tree

2 files changed

+10
-1
lines changed

2 files changed

+10
-1
lines changed

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -293,6 +293,16 @@ static DecodeStatus DecodeVRM8RegisterClass(MCInst &Inst, uint32_t RegNo,
293293
return MCDisassembler::Success;
294294
}
295295

296+
static DecodeStatus DecodeVMV0RegisterClass(MCInst &Inst, uint32_t RegNo,
297+
uint64_t Address,
298+
const MCDisassembler *Decoder) {
299+
if (RegNo)
300+
return MCDisassembler::Fail;
301+
302+
Inst.addOperand(MCOperand::createReg(RISCV::V0));
303+
return MCDisassembler::Success;
304+
}
305+
296306
static DecodeStatus decodeVMaskReg(MCInst &Inst, uint32_t RegNo,
297307
uint64_t Address,
298308
const MCDisassembler *Decoder) {

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -67,7 +67,6 @@ def VMaskOp : RegisterOperand<VMV0> {
6767
def VMaskCarryInOp : RegisterOperand<VMV0> {
6868
let ParserMatchClass = VMaskCarryInAsmOperand;
6969
let EncoderMethod = "getVMaskReg";
70-
let DecoderMethod = "decodeVMaskReg";
7170
}
7271

7372
def simm5 : RISCVSImmLeafOp<5> {

0 commit comments

Comments
 (0)