AArch64: Add tests for arm64ec for special case math functions

ldexp, frexp, and powi are a special case on windows. Annoyingly
update_llc_test_checks seems to do nothing on these lines, and
there are unrelated errors on the half cases. Also, the powi test
didn't actually emit the libcall since it was using constant values
that fold into multiplies.

Author: arsenm

llvm/test/CodeGen/AArch64/frexp-arm64ec.ll

@@ -0,0 +1,19 @@
+; RUN: llc -mtriple=arm64ec-windows-msvc < %s | FileCheck -check-prefix=ARM64EC %s
+
+; Separate from llvm-frexp.ll test because this errors on half cases
+
+; ARM64EC-LABEL: test_frexp_f32_i32
+; ARM64EC: fcvt d0, s0
+; ARM64EC: bl "#frexp"
+; ARM64EC: fcvt s0, d0
+define { float, i32 } @test_frexp_f32_i32(float %a) {
+  %result = call { float, i32 } @llvm.frexp.f32.i32(float %a)
+  ret { float, i32 } %result
+}
+
+; ARM64EC-LABEL: test_frexp_f64_i32
+; ARM64EC: bl "#frexp"
+define { double, i32 } @test_frexp_f64_i32(double %a) {
+  %result = call { double, i32 } @llvm.frexp.f64.i32(double %a)
+  ret { double, i32 } %result
+}

llvm/test/CodeGen/AArch64/ldexp-arm64ec.ll

@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=arm64ec-windows-msvc < %s | FileCheck -check-prefixes=ARM64EC %s
+
+; Separate from ldexp.ll test because this errors on half cases
+
+; ARM64EC-LABEL: ldexp_f32 =
+; ARM64EC: fcvt d0, s0
+; ARM64EC: bl "#ldexp"
+; ARM64EC: fcvt s0, d0
+define float @ldexp_f32(float %val, i32 %a) {
+  %call = call float @llvm.ldexp.f32(float %val, i32 %a)
+  ret float %call
+}
+
+; ARM64EC-LABEL: ldexp_f64 =
+; ARM64EC: b "#ldexp"
+define double @ldexp_f64(double %val, i32 %a) {
+  %call = call double @llvm.ldexp.f64(double %val, i32 %a)
+  ret double %call
+}

llvm/test/CodeGen/AArch64/powi-arm64ec.ll

@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=arm64ec-windows-msvc < %s | FileCheck -check-prefix=ARM64EC %s
+
+declare double @llvm.powi.f64.i32(double, i32)
+declare float @llvm.powi.f32.i32(float, i32)
+
+; ARM64EC-LABEL: powi_f32
+; ARM64EC: scvtf s1, w0
+; ARM64EC: b "#powf"
+define float @powi_f32(float %x, i32 %n) nounwind {
+  %ret = tail call float @llvm.powi.f32.i32(float %x, i32 %n)
+  ret float %ret
+}
+
+; ARM64EC-LABEL: powi_f64
+; ARM64EC: scvtf d1, w0
+; ARM64EC: b "#pow"
+define double @powi_f64(double %x, i32 %n) nounwind {
+  %ret = tail call double @llvm.powi.f64.i32(double %x, i32 %n)
+  ret double %ret
+}

llvm/test/CodeGen/AArch64/powi.ll

@@ -1,25 +1,65 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
+; RUN: llc -mtriple=aarch64-windows-pc-msvc < %s | FileCheck -check-prefix=WINDOWS %s
 
 declare double @llvm.powi.f64.i32(double, i32)
 declare float  @llvm.powi.f32.i32(float,  i32)
 declare float  @pow(double noundef, double noundef)
 
-define float @powi_f32(float %x) nounwind {
-; CHECK-LABEL: powi_f32:
+define float @powi_f32_4(float %x) nounwind {
+; CHECK-LABEL: powi_f32_4:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fmul s0, s0, s0
 ; CHECK-NEXT:    fmul s0, s0, s0
 ; CHECK-NEXT:    ret
+;
+; WINDOWS-LABEL: powi_f32_4:
+; WINDOWS:       // %bb.0:
+; WINDOWS-NEXT:    fmul s0, s0, s0
+; WINDOWS-NEXT:    fmul s0, s0, s0
+; WINDOWS-NEXT:    ret
   %1 = tail call float @llvm.powi.f32.i32(float %x, i32 4)
   ret float %1
 }
 
-define double @powi_f64(double %x) nounwind {
-; CHECK-LABEL: powi_f64:
+define double @powi_f64_3(double %x) nounwind {
+; CHECK-LABEL: powi_f64_3:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fmul d1, d0, d0
 ; CHECK-NEXT:    fmul d0, d0, d1
 ; CHECK-NEXT:    ret
+;
+; WINDOWS-LABEL: powi_f64_3:
+; WINDOWS:       // %bb.0:
+; WINDOWS-NEXT:    fmul d1, d0, d0
+; WINDOWS-NEXT:    fmul d0, d0, d1
+; WINDOWS-NEXT:    ret
   %1 = tail call double @llvm.powi.f64.i32(double %x, i32 3)
   ret double %1
 }
+
+define float @powi_f32(float %x, i32 %n) nounwind {
+; CHECK-LABEL: powi_f32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    b __powisf2
+;
+; WINDOWS-LABEL: powi_f32:
+; WINDOWS:       // %bb.0:
+; WINDOWS-NEXT:    scvtf s1, w0
+; WINDOWS-NEXT:    b powf
+  %ret = tail call float @llvm.powi.f32.i32(float %x, i32 %n)
+  ret float %ret
+}
+
+define double @powi_f64(double %x, i32 %n) nounwind {
+; CHECK-LABEL: powi_f64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    b __powidf2
+;
+; WINDOWS-LABEL: powi_f64:
+; WINDOWS:       // %bb.0:
+; WINDOWS-NEXT:    scvtf d1, w0
+; WINDOWS-NEXT:    b pow
+  %ret = tail call double @llvm.powi.f64.i32(double %x, i32 %n)
+  ret double %ret
+}