Update RISCVInstrInfoXqci.td

Author: svs-quic

llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td

@@ -32,13 +32,8 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
                           (ins GPR:$rs1, GPRNoX0:$rs2), "qc.csrrwr",
                           "$rd, $rs1, $rs2">;
 
-  def QC_CSRRWRI : RVInstRBase<0b000, OPC_SYSTEM, (outs GPR:$rd),
-                               (ins uimm5:$imm5, GPRNoX0:$rs2),
-                               "qc.csrrwri", "$rd, $imm5, $rs2"> {
-    bits<5> imm5;
-
-    let Inst{31-25} = {0b1000111};
-    let Inst{19-15} = imm5;
-  }
+  def QC_CSRRWRI : RVInstR<0b1000111, 0b000, OPC_SYSTEM, (outs GPR:$rd),
+                           (ins uimm5:$rs1, GPRNoX0:$rs2), "qc.csrrwri",
+                           "$rd, $rs1, $rs2">;
 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0
 } // Predicates = [HasVendorXqcicsr, IsRV32], DecoderNamespace = "Xqcicsr"