Skip to content

Commit 40a9e34

Browse files
jthackrayrgwott
jthackray
and
rgwott
authored
[AArch64][llvm] Add support for Permission Overlay Extension 2 (FEAT_S1POE2) (#164912)
Add assembly/disassembly support for AArch64 `FEAT_S1POE2` (Stage 1 Permission Overlay Extension 2), as blogged about here: * https://developer.arm.com/community/arm-community-blogs/b/architectures-and-processors-blog/posts/future-architecture-technologies-poe2-and-vmte and as documented here: * https://developer.arm.com/documentation/109697/2025_09/Future-Architecture-Technologies Co-authored-by: Rodolfo Wottrich <[email protected]>
1 parent 8723fe5 commit 40a9e34

18 files changed

+3961
-6
lines changed

‎clang/test/Driver/aarch64-vfat.c‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,3 +5,15 @@
55
// RUN: %clang -target aarch64 -march=armv9.7a+mops-go -### -c %s 2>&1 | FileCheck -check-prefix=VFAT-MOPS-GO %s
66
// RUN: %clang -target aarch64 -march=armv9.7-a+mops-go -### -c %s 2>&1 | FileCheck -check-prefix=VFAT-MOPS-GO %s
77
// VFAT-MOPS-GO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.7a"{{.*}} "-target-feature" "+mops-go"
8+
9+
// RUN: %clang -target aarch64 -march=armv9.7a+poe2 -### -c %s 2>&1 | FileCheck -check-prefix=VFAT-POE2 %s
10+
// RUN: %clang -target aarch64 -march=armv9.7-a+poe2 -### -c %s 2>&1 | FileCheck -check-prefix=VFAT-POE2 %s
11+
// VFAT-POE2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.7a"{{.*}} "-target-feature" "+poe2"
12+
13+
// RUN: %clang -target aarch64 -march=armv9.7a+tev -### -c %s 2>&1 | FileCheck -check-prefix=VFAT-TEV %s
14+
// RUN: %clang -target aarch64 -march=armv9.7-a+tev -### -c %s 2>&1 | FileCheck -check-prefix=VFAT-TEV %s
15+
// VFAT-TEV: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.7a"{{.*}} "-target-feature" "+tev"
16+
17+
// RUN: %clang -target aarch64 -march=armv9.7a+btie -### -c %s 2>&1 | FileCheck -check-prefix=VFAT-BTIE %s
18+
// RUN: %clang -target aarch64 -march=armv9.7-a+btie -### -c %s 2>&1 | FileCheck -check-prefix=VFAT-BTIE %s
19+
// VFAT-BTIE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.7a"{{.*}} "-target-feature" "+btie"

‎clang/test/Driver/print-supported-extensions-aarch64.c‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@
88
// CHECK-NEXT: bf16 FEAT_BF16 Enable BFloat16 Extension
99
// CHECK-NEXT: brbe FEAT_BRBE Enable Branch Record Buffer Extension
1010
// CHECK-NEXT: bti FEAT_BTI Enable Branch Target Identification
11+
// CHECK-NEXT: btie FEAT_BTIE Enable Enhanced Branch Target Identification extension
1112
// CHECK-NEXT: cmh FEAT_CMH Enable Armv9.7-A Contention Management Hints
1213
// CHECK-NEXT: cmpbr FEAT_CMPBR Enable Armv9.6-A base compare and branch instructions
1314
// CHECK-NEXT: fcma FEAT_FCMA Enable Armv8.3-A Floating-point complex number support
@@ -59,6 +60,7 @@
5960
// CHECK-NEXT: pauth-lr FEAT_PAuth_LR Enable Armv9.5-A PAC enhancements
6061
// CHECK-NEXT: pcdphint FEAT_PCDPHINT Enable Armv9.6-A Producer Consumer Data Placement hints
6162
// CHECK-NEXT: pmuv3 FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
63+
// CHECK-NEXT: poe2 FEAT_S1POE2 Enable Stage 1 Permission Overlays Extension 2 instructions
6264
// CHECK-NEXT: pops FEAT_PoPS Enable Armv9.6-A Point Of Physical Storage (PoPS) DC instructions
6365
// CHECK-NEXT: predres FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions
6466
// CHECK-NEXT: rng FEAT_RNG Enable Random Number generation instructions
@@ -113,6 +115,7 @@
113115
// CHECK-NEXT: sve2p1 FEAT_SVE2p1 Enable Scalable Vector Extension 2.1 instructions
114116
// CHECK-NEXT: sve2p2 FEAT_SVE2p2 Enable Armv9.6-A Scalable Vector Extension 2.2 instructions
115117
// CHECK-NEXT: sve2p3 FEAT_SVE2p3 Enable Armv9.7-A Scalable Vector Extension 2.3 instructions
118+
// CHECK-NEXT: tev FEAT_TEV Enable TIndex Exception-like Vector instructions
116119
// CHECK-NEXT: the FEAT_THE Enable Armv8.9-A Translation Hardening Extension
117120
// CHECK-NEXT: tlbid FEAT_TLBID Enable Armv9.7-A TLBI Domains extension
118121
// CHECK-NEXT: tlbiw FEAT_TLBIW Enable Armv9.5-A TLBI VMALL for Dirty State

‎llvm/docs/ReleaseNotes.md‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -105,7 +105,8 @@ Changes to the AArch64 Backend
105105
architecture extensions.
106106

107107
* Assembler/disassembler support has been added for 'Virtual Tagging
108-
Extension (vMTE)' Future Architecture Technologies extension.
108+
Extension (vMTE)' and 'Permission Overlay Extension version 2 (POE2)'
109+
Future Architecture Technologies extensions.
109110

110111
Changes to the AMDGPU Backend
111112
-----------------------------

‎llvm/lib/Target/AArch64/AArch64Features.td‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -632,6 +632,15 @@ def FeatureF16F32MM : ExtensionWithMArch<"f16f32mm", "F16F32MM", "FEAT_F16F32MM"
632632
def FeatureMOPS_GO: ExtensionWithMArch<"mops-go", "MOPS_GO", "FEAT_MOPS_GO",
633633
"Enable memset acceleration granule only">;
634634

635+
def FeatureBTIE: ExtensionWithMArch<"btie", "BTIE", "FEAT_BTIE",
636+
"Enable Enhanced Branch Target Identification extension">;
637+
638+
def FeatureS1POE2: ExtensionWithMArch<"poe2", "POE2", "FEAT_S1POE2",
639+
"Enable Stage 1 Permission Overlays Extension 2 instructions">;
640+
641+
def FeatureTEV: ExtensionWithMArch<"tev", "TEV", "FEAT_TEV",
642+
"Enable TIndex Exception-like Vector instructions">;
643+
635644
//===----------------------------------------------------------------------===//
636645
// Other Features
637646
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AArch64/AArch64InstrFormats.td‎

Lines changed: 96 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1909,6 +1909,21 @@ def CMHPriorityHint_op : Operand<i32> {
19091909
}];
19101910
}
19111911

1912+
def TIndexHintOperand : AsmOperandClass {
1913+
let Name = "TIndexHint";
1914+
let ParserMethod = "tryParseTIndexHint";
1915+
}
1916+
1917+
def TIndexhint_op : Operand<i32> {
1918+
let ParserMatchClass = TIndexHintOperand;
1919+
let PrintMethod = "printTIndexHintOp";
1920+
let MCOperandPredicate = [{
1921+
if (!MCOp.isImm())
1922+
return false;
1923+
return AArch64TIndexHint::lookupTIndexByEncoding(MCOp.getImm()) != nullptr;
1924+
}];
1925+
}
1926+
19121927
class MRSI : RtSystemI<1, (outs GPR64:$Rt), (ins mrs_sysreg_op:$systemreg),
19131928
"mrs", "\t$Rt, $systemreg"> {
19141929
bits<16> systemreg;
@@ -13366,3 +13381,84 @@ class STCPHInst<string asm> : I<
1336613381
let Inst{7-5} = 0b100;
1336713382
let Inst{4-0} = 0b11111;
1336813383
}
13384+
13385+
//---
13386+
// Permission Overlays Extension 2 (FEAT_S1POE2)
13387+
//---
13388+
13389+
class TCHANGERegInst<string asm, bit isB> : I<
13390+
(outs GPR64:$Xd),
13391+
(ins GPR64:$Xn, TIndexhint_op:$nb),
13392+
asm, "\t$Xd, $Xn, $nb", "", []>, Sched<[]> {
13393+
bits<5> Xd;
13394+
bits<5> Xn;
13395+
bits<1> nb;
13396+
let Inst{31-19} = 0b1101010110000;
13397+
let Inst{18} = isB;
13398+
let Inst{17} = nb;
13399+
let Inst{16-10} = 0b0000000;
13400+
let Inst{9-5} = Xn;
13401+
let Inst{4-0} = Xd;
13402+
}
13403+
13404+
class TCHANGEImmInst<string asm, bit isB> : I<
13405+
(outs GPR64:$Xd),
13406+
(ins imm0_127:$imm, TIndexhint_op:$nb),
13407+
asm, "\t$Xd, $imm, $nb", "", []>, Sched<[]> {
13408+
bits<5> Xd;
13409+
bits<7> imm;
13410+
bits<1> nb;
13411+
let Inst{31-19} = 0b1101010110010;
13412+
let Inst{18} = isB;
13413+
let Inst{17} = nb;
13414+
let Inst{16-12} = 0b00000;
13415+
let Inst{11-5} = imm;
13416+
let Inst{4-0} = Xd;
13417+
}
13418+
13419+
class TENTERInst<string asm> : I<
13420+
(outs),
13421+
(ins imm0_127:$imm, TIndexhint_op:$nb),
13422+
asm, "\t$imm, $nb", "", []>, Sched<[]> {
13423+
bits<7> imm;
13424+
bits<1> nb;
13425+
let Inst{31-18} = 0b11010100111000;
13426+
let Inst{17} = nb;
13427+
let Inst{16-12} = 0b00000;
13428+
let Inst{11-5} = imm;
13429+
let Inst{4-0} = 0b00000;
13430+
}
13431+
13432+
class TEXITInst<string asm> : I<
13433+
(outs),
13434+
(ins TIndexhint_op:$nb),
13435+
asm, "\t$nb", "", []>, Sched<[]> {
13436+
bits<1> nb;
13437+
let Inst{31-11} = 0b110101101111111100000;
13438+
let Inst{10} = nb;
13439+
let Inst{9-0} = 0b1111100000;
13440+
}
13441+
13442+
13443+
multiclass TCHANGEReg<string asm , bit isB> {
13444+
def NAME : TCHANGERegInst<asm, isB>;
13445+
def : InstAlias<asm # "\t$Xd, $Xn",
13446+
(!cast<Instruction>(NAME) GPR64:$Xd, GPR64:$Xn, 0), 1>;
13447+
}
13448+
13449+
multiclass TCHANGEImm<string asm, bit isB> {
13450+
def NAME : TCHANGEImmInst<asm, isB>;
13451+
def : InstAlias<asm # "\t$Xd, $imm",
13452+
(!cast<Instruction>(NAME) GPR64:$Xd, imm0_127:$imm, 0), 1>;
13453+
}
13454+
13455+
multiclass TENTER<string asm> {
13456+
def NAME : TENTERInst<asm>;
13457+
def : InstAlias<asm # "\t$imm",
13458+
(!cast<Instruction>(NAME) imm0_127:$imm, 0), 1>;
13459+
}
13460+
13461+
multiclass TEXIT<string asm> {
13462+
def NAME : TEXITInst<asm>;
13463+
def : InstAlias<asm, (!cast<Instruction>(NAME) 0), 1>;
13464+
}

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td‎

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -346,6 +346,8 @@ def HasCCDP : Predicate<"Subtarget->hasCCDP()">,
346346
AssemblerPredicateWithAll<(all_of FeatureCacheDeepPersist), "ccdp">;
347347
def HasBTI : Predicate<"Subtarget->hasBTI()">,
348348
AssemblerPredicateWithAll<(all_of FeatureBranchTargetId), "bti">;
349+
def HasBTIE : Predicate<"Subtarget->hasBTIE()">,
350+
AssemblerPredicateWithAll<(all_of FeatureBTIE), "btie">;
349351
def HasMTE : Predicate<"Subtarget->hasMTE()">,
350352
AssemblerPredicateWithAll<(all_of FeatureMTE), "mte">;
351353
def HasTME : Predicate<"Subtarget->hasTME()">,
@@ -407,6 +409,10 @@ def HasGCIE : Predicate<"Subtarget->hasGCIE()">,
407409
AssemblerPredicateWithAll<(all_of FeatureGCIE), "gcie">;
408410
def HasMOPS_GO : Predicate<"Subtarget->hasMOPS_GO()">,
409411
AssemblerPredicateWithAll<(all_of FeatureMOPS_GO), "mops-go">;
412+
def HasS1POE2 : Predicate<"Subtarget->hasS1POE2()">,
413+
AssemblerPredicateWithAll<(all_of FeatureS1POE2), "poe2">;
414+
def HasTEV : Predicate<"Subtarget->hasTEV()">,
415+
AssemblerPredicateWithAll<(all_of FeatureTEV), "tev">;
410416
def IsLE : Predicate<"Subtarget->isLittleEndian()">;
411417
def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
412418
def IsWindows : Predicate<"Subtarget->isTargetWindows()">;
@@ -1542,6 +1548,7 @@ let Predicates = [HasPCDPHINT] in {
15421548
// should not emit these mnemonics unless BTI is enabled.
15431549
def : InstAlias<"bti", (HINT 32), 0>;
15441550
def : InstAlias<"bti $op", (HINT btihint_op:$op), 0>;
1551+
def : InstAlias<"bti r", (HINT 32)>, Requires<[HasBTIE]>;
15451552
def : InstAlias<"bti", (HINT 32)>, Requires<[HasBTI]>;
15461553
def : InstAlias<"bti $op", (HINT btihint_op:$op)>, Requires<[HasBTI]>;
15471554

@@ -11444,6 +11451,26 @@ let Predicates = [HasCMH] in {
1144411451
def STCPH : STCPHInst<"stcph">; // Store Concurrent Priority Hint instruction
1144511452
}
1144611453

11454+
//===----------------------------------------------------------------------===//
11455+
// Permission Overlays Extension 2 (FEAT_S1POE2)
11456+
//===----------------------------------------------------------------------===//
11457+
11458+
let Predicates = [HasS1POE2] in {
11459+
defm TCHANGEBrr : TCHANGEReg<"tchangeb", true>;
11460+
defm TCHANGEFrr : TCHANGEReg<"tchangef", false>;
11461+
defm TCHANGEBri : TCHANGEImm<"tchangeb", true>;
11462+
defm TCHANGEFri : TCHANGEImm<"tchangef", false>;
11463+
}
11464+
11465+
//===----------------------------------------------------------------------===//
11466+
// TIndex Exception-like Vector (FEAT_TEV)
11467+
//===----------------------------------------------------------------------===//
11468+
11469+
let Predicates = [HasTEV] in {
11470+
defm TENTER : TENTER<"tenter">;
11471+
defm TEXIT : TEXIT<"texit">;
11472+
}
11473+
1144711474
include "AArch64InstrAtomics.td"
1144811475
include "AArch64SVEInstrInfo.td"
1144911476
include "AArch64SMEInstrInfo.td"

0 commit comments

Comments
 (0)