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michaelmaitlandmichaelmaitland
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[RISCV][GISEL] Generate VLMax using -1 constant (#110778)
SelectionDAG uses ISD::REGISTER and uses RISCV::X0 to represent VLMAX. Then in ComplexPattern VLOpt uses selectVLOp to convert RISCV::X0 to RISCV::VLMaxSentinel. The original legalization patch for G_SPLAT_VECTOR used Register RISCV::X0 directly. $x0 has no LLT type, so GIComplexOperandMatcher has no way of matching. The approach we are changing to here will allow us to successfully use GIComplexOperandMatcher to implement the ComplexMatcherFn selectVLOp in GISEL since the operand now has a type.
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lines changed

10 files changed

+409
-258
lines changed

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp‎

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -833,19 +833,21 @@ static MachineInstrBuilder buildAllOnesMask(LLT VecTy, const SrcOp &VL,
833833

834834
/// Gets the two common "VL" operands: an all-ones mask and the vector length.
835835
/// VecTy is a scalable vector type.
836-
static std::pair<MachineInstrBuilder, Register>
836+
static std::pair<MachineInstrBuilder, MachineInstrBuilder>
837837
buildDefaultVLOps(const DstOp &Dst, MachineIRBuilder &MIB,
838838
MachineRegisterInfo &MRI) {
839839
LLT VecTy = Dst.getLLTTy(MRI);
840840
assert(VecTy.isScalableVector() && "Expecting scalable container type");
841-
Register VL(RISCV::X0);
842-
MachineInstrBuilder Mask = buildAllOnesMask(VecTy, VL, MIB, MRI);
841+
const RISCVSubtarget &STI = MIB.getMF().getSubtarget<RISCVSubtarget>();
842+
LLT XLenTy(STI.getXLenVT());
843+
auto VL = MIB.buildConstant(XLenTy, -1);
844+
auto Mask = buildAllOnesMask(VecTy, VL, MIB, MRI);
843845
return {Mask, VL};
844846
}
845847

846848
static MachineInstrBuilder
847849
buildSplatPartsS64WithVL(const DstOp &Dst, const SrcOp &Passthru, Register Lo,
848-
Register Hi, Register VL, MachineIRBuilder &MIB,
850+
Register Hi, const SrcOp &VL, MachineIRBuilder &MIB,
849851
MachineRegisterInfo &MRI) {
850852
// TODO: If the Hi bits of the splat are undefined, then it's fine to just
851853
// splat Lo even if it might be sign extended. I don't think we have
@@ -861,7 +863,7 @@ buildSplatPartsS64WithVL(const DstOp &Dst, const SrcOp &Passthru, Register Lo,
861863

862864
static MachineInstrBuilder
863865
buildSplatSplitS64WithVL(const DstOp &Dst, const SrcOp &Passthru,
864-
const SrcOp &Scalar, Register VL,
866+
const SrcOp &Scalar, const SrcOp &VL,
865867
MachineIRBuilder &MIB, MachineRegisterInfo &MRI) {
866868
assert(Scalar.getLLTTy(MRI) == LLT::scalar(64) && "Unexpected VecTy!");
867869
auto Unmerge = MIB.buildUnmerge(LLT::scalar(32), Scalar);

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-constbarrier-rv32.mir‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -52,8 +52,9 @@ name: constbarrier_nxv2i1
5252
body: |
5353
bb.0.entry:
5454
; CHECK-LABEL: name: constbarrier_nxv2i1
55-
; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL $x0
56-
; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMCLR_VL $x0
55+
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
56+
; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C]](s32)
57+
; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMCLR_VL [[C]](s32)
5758
; CHECK-NEXT: [[CONSTANT_FOLD_BARRIER:%[0-9]+]]:_(<vscale x 2 x s1>) = G_CONSTANT_FOLD_BARRIER [[VMCLR_VL]]
5859
; CHECK-NEXT: $v8 = COPY [[CONSTANT_FOLD_BARRIER]](<vscale x 2 x s1>)
5960
; CHECK-NEXT: PseudoRET implicit $v8

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-constbarrier-rv64.mir‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -70,8 +70,9 @@ name: constbarrier_nxv2i1
7070
body: |
7171
bb.0.entry:
7272
; CHECK-LABEL: name: constbarrier_nxv2i1
73-
; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL $x0
74-
; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMCLR_VL $x0
73+
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
74+
; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C]](s64)
75+
; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMCLR_VL [[C]](s64)
7576
; CHECK-NEXT: [[CONSTANT_FOLD_BARRIER:%[0-9]+]]:_(<vscale x 2 x s1>) = G_CONSTANT_FOLD_BARRIER [[VMCLR_VL]]
7677
; CHECK-NEXT: $v8 = COPY [[CONSTANT_FOLD_BARRIER]](<vscale x 2 x s1>)
7778
; CHECK-NEXT: PseudoRET implicit $v8

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-extract-subvector.mir‎

Lines changed: 50 additions & 36 deletions
Large diffs are not rendered by default.

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-rv32.mir‎

Lines changed: 42 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -8,8 +8,9 @@ tracksRegLiveness: true
88
body: |
99
bb.1:
1010
; CHECK-LABEL: name: splatvector_nxv1i1_0
11-
; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL $x0
12-
; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMCLR_VL $x0
11+
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
12+
; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C]](s32)
13+
; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMCLR_VL [[C]](s32)
1314
; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 1 x s1>)
1415
; CHECK-NEXT: PseudoRET implicit $v0
1516
%0:_(s1) = G_CONSTANT i1 0
@@ -25,8 +26,9 @@ tracksRegLiveness: true
2526
body: |
2627
bb.1:
2728
; CHECK-LABEL: name: splatvector_nxv1i1_1
28-
; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL $x0
29-
; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL $x0
29+
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
30+
; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C]](s32)
31+
; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C]](s32)
3032
; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 1 x s1>)
3133
; CHECK-NEXT: PseudoRET implicit $v0
3234
%0:_(s1) = G_CONSTANT i1 1
@@ -69,8 +71,9 @@ tracksRegLiveness: true
6971
body: |
7072
bb.1:
7173
; CHECK-LABEL: name: splatvector_nxv2i1_0
72-
; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL $x0
73-
; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMCLR_VL $x0
74+
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
75+
; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C]](s32)
76+
; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMCLR_VL [[C]](s32)
7477
; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 2 x s1>)
7578
; CHECK-NEXT: PseudoRET implicit $v0
7679
%0:_(s1) = G_CONSTANT i1 0
@@ -86,8 +89,9 @@ tracksRegLiveness: true
8689
body: |
8790
bb.1:
8891
; CHECK-LABEL: name: splatvector_nxv2i1_1
89-
; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL $x0
90-
; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL $x0
92+
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
93+
; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C]](s32)
94+
; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C]](s32)
9195
; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 2 x s1>)
9296
; CHECK-NEXT: PseudoRET implicit $v0
9397
%0:_(s1) = G_CONSTANT i1 1
@@ -130,8 +134,9 @@ tracksRegLiveness: true
130134
body: |
131135
bb.1:
132136
; CHECK-LABEL: name: splatvector_nxv4i1_0
133-
; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL $x0
134-
; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMCLR_VL $x0
137+
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
138+
; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C]](s32)
139+
; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMCLR_VL [[C]](s32)
135140
; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 4 x s1>)
136141
; CHECK-NEXT: PseudoRET implicit $v0
137142
%0:_(s1) = G_CONSTANT i1 0
@@ -147,8 +152,9 @@ tracksRegLiveness: true
147152
body: |
148153
bb.1:
149154
; CHECK-LABEL: name: splatvector_nxv4i1_1
150-
; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL $x0
151-
; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL $x0
155+
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
156+
; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C]](s32)
157+
; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C]](s32)
152158
; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 4 x s1>)
153159
; CHECK-NEXT: PseudoRET implicit $v0
154160
%0:_(s1) = G_CONSTANT i1 1
@@ -191,8 +197,9 @@ tracksRegLiveness: true
191197
body: |
192198
bb.1:
193199
; CHECK-LABEL: name: splatvector_nxv8i1_0
194-
; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL $x0
195-
; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMCLR_VL $x0
200+
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
201+
; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL [[C]](s32)
202+
; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMCLR_VL [[C]](s32)
196203
; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 8 x s1>)
197204
; CHECK-NEXT: PseudoRET implicit $v0
198205
%0:_(s1) = G_CONSTANT i1 0
@@ -208,8 +215,9 @@ tracksRegLiveness: true
208215
body: |
209216
bb.1:
210217
; CHECK-LABEL: name: splatvector_nxv8i1_1
211-
; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL $x0
212-
; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL $x0
218+
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
219+
; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL [[C]](s32)
220+
; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL [[C]](s32)
213221
; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 8 x s1>)
214222
; CHECK-NEXT: PseudoRET implicit $v0
215223
%0:_(s1) = G_CONSTANT i1 1
@@ -252,8 +260,9 @@ tracksRegLiveness: true
252260
body: |
253261
bb.1:
254262
; CHECK-LABEL: name: splatvector_nxv16i1_0
255-
; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMSET_VL $x0
256-
; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMCLR_VL $x0
263+
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
264+
; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMSET_VL [[C]](s32)
265+
; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMCLR_VL [[C]](s32)
257266
; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 16 x s1>)
258267
; CHECK-NEXT: PseudoRET implicit $v0
259268
%0:_(s1) = G_CONSTANT i1 0
@@ -269,8 +278,9 @@ tracksRegLiveness: true
269278
body: |
270279
bb.1:
271280
; CHECK-LABEL: name: splatvector_nxv16i1_1
272-
; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMSET_VL $x0
273-
; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMSET_VL $x0
281+
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
282+
; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMSET_VL [[C]](s32)
283+
; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 16 x s1>) = G_VMSET_VL [[C]](s32)
274284
; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 16 x s1>)
275285
; CHECK-NEXT: PseudoRET implicit $v0
276286
%0:_(s1) = G_CONSTANT i1 1
@@ -313,8 +323,9 @@ tracksRegLiveness: true
313323
body: |
314324
bb.1:
315325
; CHECK-LABEL: name: splatvector_nxv32i1_0
316-
; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 32 x s1>) = G_VMSET_VL $x0
317-
; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 32 x s1>) = G_VMCLR_VL $x0
326+
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
327+
; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 32 x s1>) = G_VMSET_VL [[C]](s32)
328+
; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 32 x s1>) = G_VMCLR_VL [[C]](s32)
318329
; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 32 x s1>)
319330
; CHECK-NEXT: PseudoRET implicit $v0
320331
%0:_(s1) = G_CONSTANT i1 0
@@ -330,8 +341,9 @@ tracksRegLiveness: true
330341
body: |
331342
bb.1:
332343
; CHECK-LABEL: name: splatvector_nxv32i1_1
333-
; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 32 x s1>) = G_VMSET_VL $x0
334-
; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 32 x s1>) = G_VMSET_VL $x0
344+
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
345+
; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 32 x s1>) = G_VMSET_VL [[C]](s32)
346+
; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 32 x s1>) = G_VMSET_VL [[C]](s32)
335347
; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 32 x s1>)
336348
; CHECK-NEXT: PseudoRET implicit $v0
337349
%0:_(s1) = G_CONSTANT i1 1
@@ -374,8 +386,9 @@ tracksRegLiveness: true
374386
body: |
375387
bb.1:
376388
; CHECK-LABEL: name: splatvector_nxv64i1_0
377-
; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 64 x s1>) = G_VMSET_VL $x0
378-
; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 64 x s1>) = G_VMCLR_VL $x0
389+
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
390+
; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 64 x s1>) = G_VMSET_VL [[C]](s32)
391+
; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:_(<vscale x 64 x s1>) = G_VMCLR_VL [[C]](s32)
379392
; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 64 x s1>)
380393
; CHECK-NEXT: PseudoRET implicit $v0
381394
%0:_(s1) = G_CONSTANT i1 0
@@ -391,8 +404,9 @@ tracksRegLiveness: true
391404
body: |
392405
bb.1:
393406
; CHECK-LABEL: name: splatvector_nxv64i1_1
394-
; CHECK: [[VMSET_VL:%[0-9]+]]:_(<vscale x 64 x s1>) = G_VMSET_VL $x0
395-
; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 64 x s1>) = G_VMSET_VL $x0
407+
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
408+
; CHECK-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 64 x s1>) = G_VMSET_VL [[C]](s32)
409+
; CHECK-NEXT: [[VMSET_VL1:%[0-9]+]]:_(<vscale x 64 x s1>) = G_VMSET_VL [[C]](s32)
396410
; CHECK-NEXT: $v0 = COPY [[VMSET_VL1]](<vscale x 64 x s1>)
397411
; CHECK-NEXT: PseudoRET implicit $v0
398412
%0:_(s1) = G_CONSTANT i1 1

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