@@ -8716,11 +8716,9 @@ void SIInstrInfo::splitScalar64BitCountOp(SIInstrWorklist &Worklist,
87168716void SIInstrInfo::addUsersToMoveToVALUWorklist (
87178717 Register DstReg, MachineRegisterInfo &MRI,
87188718 SIInstrWorklist &Worklist) const {
8719- SmallVector<std::pair<MachineInstr *, unsigned >> EarlyRangeInc;
8720-
8721- for (MachineRegisterInfo::use_iterator I = MRI.use_begin (DstReg),
8722- E = MRI.use_end (); I != E;) {
8723- MachineInstr &UseMI = *I->getParent ();
8719+ MachineInstr *prevMI = nullptr ;
8720+ for (MachineOperand &MO : make_early_inc_range (MRI.use_operands (DstReg))) {
8721+ MachineInstr &UseMI = *MO.getParent ();
87248722
87258723 unsigned OpNo = 0 ;
87268724
@@ -8735,25 +8733,22 @@ void SIInstrInfo::addUsersToMoveToVALUWorklist(
87358733 case AMDGPU::INSERT_SUBREG:
87368734 break ;
87378735 default :
8738- OpNo = I .getOperandNo ();
8736+ OpNo = MO .getOperandNo ();
87398737 break ;
87408738 }
87418739
87428740 if (!RI.hasVectorRegisters (getOpRegClass (UseMI, OpNo))) {
8743- Worklist.insert (&UseMI);
8741+ if (&UseMI == prevMI)
8742+ continue ;
87448743
8745- do {
8746- ++I;
8747- } while (I != E && I->getParent () == &UseMI);
8748- } else {
8749- EarlyRangeInc.emplace_back (&UseMI, OpNo);
8744+ prevMI = &UseMI;
87508745
8751- ++I;
8746+ Worklist.insert (&UseMI);
8747+ } else {
8748+ // legalize could changes user list
8749+ legalizeOperandsVALUt16 (UseMI, OpNo, MRI);
87528750 }
87538751 }
8754-
8755- for (auto &[UseMI, OpNo] : EarlyRangeInc)
8756- legalizeOperandsVALUt16 (*UseMI, OpNo, MRI);
87578752}
87588753
87598754void SIInstrInfo::movePackToVALU (SIInstrWorklist &Worklist,
0 commit comments