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[FMV][AArch64] Unify features ssbs and ssbs2. (#110297)
According to https://developer.arm.com/documentation/102105/latest Arm Architecture Reference Manual for A-profile architecture: Known issues 2.206 D22789 In section C5.2.25 "SSBS, Speculative Store Bypass Safe", under the heading 'Configurations', the text that reads: "This register is present only when FEAT_SSBS is implemented. Otherwise, direct accesses to SSBS are UNDEFINED." is changed to read: "This register is present only when FEAT_SSBS2 is implemented. Otherwise, direct accesses to SSBS are UNDEFINED." This suggests that it's not worth splitting FEAT_SSBS2 from FEAT_SSBS in the compiler, since FEAT_SSBS cannot be used for predicating the MRS/MSR instructions. Those can access PSTATE.SSBS only when FEAT_SSBS2 is available. Moreover, there are no hardware implementations which implement FEAT_SSBS without FEAT_SSBS2, therefore unifying these features in the specification should not be a regression for feature detection. Approved in ACLE as ARM-software/acle#350
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‎clang/test/CodeGen/aarch64-fmv-dependencies.c‎

Lines changed: 2 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -135,12 +135,9 @@ __attribute__((target_version("sme-i16i64"))) int fmv(void) { return 0; }
135135
// CHECK: define dso_local i32 @fmv._Msme2() #[[sme2:[0-9]+]] {
136136
__attribute__((target_version("sme2"))) int fmv(void) { return 0; }
137137

138-
// CHECK: define dso_local i32 @fmv._Mssbs() #[[ATTR0:[0-9]+]] {
138+
// CHECK: define dso_local i32 @fmv._Mssbs() #[[ssbs:[0-9]+]] {
139139
__attribute__((target_version("ssbs"))) int fmv(void) { return 0; }
140140

141-
// CHECK: define dso_local i32 @fmv._Mssbs2() #[[ssbs2:[0-9]+]] {
142-
__attribute__((target_version("ssbs2"))) int fmv(void) { return 0; }
143-
144141
// CHECK: define dso_local i32 @fmv._Msve() #[[sve:[0-9]+]] {
145142
__attribute__((target_version("sve"))) int fmv(void) { return 0; }
146143

@@ -219,7 +216,7 @@ int caller() {
219216
// CHECK: attributes #[[sme_f64f64]] = { {{.*}} "target-features"="+bf16,+fp-armv8,+neon,+outline-atomics,+sme,+sme-f64f64,+v8a"
220217
// CHECK: attributes #[[sme_i16i64]] = { {{.*}} "target-features"="+bf16,+fp-armv8,+neon,+outline-atomics,+sme,+sme-i16i64,+v8a"
221218
// CHECK: attributes #[[sme2]] = { {{.*}} "target-features"="+bf16,+fp-armv8,+neon,+outline-atomics,+sme,+sme2,+v8a"
222-
// CHECK: attributes #[[ssbs2]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+ssbs,+v8a"
219+
// CHECK: attributes #[[ssbs]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+ssbs,+v8a"
223220
// CHECK: attributes #[[sve]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+v8a"
224221
// CHECK: attributes #[[sve_bf16_ebf16]] = { {{.*}} "target-features"="+bf16,+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+v8a"
225222
// CHECK: attributes #[[sve_i8mm]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+i8mm,+neon,+outline-atomics,+sve,+v8a"

‎clang/test/CodeGen/attr-target-version.c‎

Lines changed: 52 additions & 51 deletions
Large diffs are not rendered by default.

‎clang/test/CodeGenCXX/attr-target-clones-aarch64.cpp‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -173,8 +173,8 @@ void run_foo_tml() {
173173
// CHECK-NEXT: [[RESOLVER_ENTRY:.*:]]
174174
// CHECK-NEXT: call void @__init_cpu_features_resolver()
175175
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
176-
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 36310271995674624
177-
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 36310271995674624
176+
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 36591746972385280
177+
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 36591746972385280
178178
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
179179
// CHECK-NEXT: br i1 [[TMP3]], label %[[RESOLVER_RETURN:.*]], label %[[RESOLVER_ELSE:.*]]
180180
// CHECK: [[RESOLVER_RETURN]]:
@@ -222,8 +222,8 @@ void run_foo_tml() {
222222
// CHECK-NEXT: [[RESOLVER_ENTRY:.*:]]
223223
// CHECK-NEXT: call void @__init_cpu_features_resolver()
224224
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
225-
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 36310271995674624
226-
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 36310271995674624
225+
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 36591746972385280
226+
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 36591746972385280
227227
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
228228
// CHECK-NEXT: br i1 [[TMP3]], label %[[RESOLVER_RETURN:.*]], label %[[RESOLVER_ELSE:.*]]
229229
// CHECK: [[RESOLVER_RETURN]]:
@@ -243,7 +243,7 @@ void run_foo_tml() {
243243
// CHECK: attributes #[[ATTR0]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+ls64,+neon" }
244244
// CHECK: attributes #[[ATTR1]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
245245
// CHECK: attributes #[[ATTR2]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fptoint" }
246-
// CHECK: attributes #[[ATTR3]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sme,+sme-f64f64" }
246+
// CHECK: attributes #[[ATTR3]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sme,+sme-f64f64,+ssbs" }
247247
//.
248248
// CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
249249
// CHECK: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}

‎clang/test/Sema/attr-target-clones-aarch64.c‎

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -4,8 +4,6 @@ void __attribute__((target_clones("fp16+sve2-aes", "sb+sve2-sha3+rcpc3+mops", "r
44

55
// expected-warning@+1 {{unsupported 'default' in the 'target_clones' attribute string; 'target_clones' attribute ignored}}
66
void __attribute__((target_clones("default+sha3"))) warn1(void);
7-
// expected-warning@+1 {{version list contains entries that don't impact code generation}}
8-
void __attribute__((target_clones("ssbs"))) warn2(void);
97

108
// expected-error@+2 {{'target_clones' and 'target_version' attributes are not compatible}}
119
// expected-note@+1 {{conflicting attribute is here}}
@@ -49,7 +47,6 @@ int __attribute__((target_clones("fp", "fp", "crc+dotprod", "dotprod+crc"))) dup
4947

5048
// expected-warning@+1 {{version list contains duplicate entries}}
5149
int __attribute__((target_clones("fp16+memtag", "memtag+fp16"))) dup6(void) { return 6; }
52-
int __attribute__((target_clones("simd+ssbs2", "simd+dpb2"))) dup7(void) { return 7; }
5350

5451
// expected-warning@+1 {{unsupported '' in the 'target_clones' attribute string;}}
5552
void __attribute__((target_clones(""))) empty_target_1(void);
@@ -79,6 +76,6 @@ int useage(void) {
7976
return mv_after_use();
8077
}
8178
// expected-error@+1 {{function declaration cannot become a multiversioned function after first usage}}
82-
int __attribute__((target_clones("sve2-sha3+ssbs2", "sm4"))) mv_after_use(void) { return 1; }
79+
int __attribute__((target_clones("sve2-sha3+ssbs", "sm4"))) mv_after_use(void) { return 1; }
8380
// expected-error@+1 {{'main' cannot be a multiversioned function}}
8481
int __attribute__((target_clones("sve-i8mm"))) main() { return 1; }

‎clang/test/SemaCXX/attr-target-version.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -99,10 +99,10 @@ __attribute__((target_version("jscvt"))) void Decl();
9999

100100
class Out { // #defined-here
101101
int __attribute__((target_version("bti"))) func(void);
102-
int __attribute__((target_version("ssbs2"))) func(void);
102+
int __attribute__((target_version("ssbs"))) func(void);
103103
};
104104
int __attribute__((target_version("bti"))) Out::func(void) { return 1; }
105-
int __attribute__((target_version("ssbs2"))) Out::func(void) { return 2; }
105+
int __attribute__((target_version("ssbs"))) Out::func(void) { return 2; }
106106
// expected-error@+4 {{out-of-line definition of 'func' does not match any declaration in 'Out'}}
107107
// expected-note@-2 {{member declaration nearly matches}}
108108
// expected-note@-4 {{member declaration nearly matches}}

‎compiler-rt/lib/builtins/cpu_model/AArch64CPUFeatures.inc‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -70,7 +70,7 @@ enum CPUFeatures {
7070
FEAT_MEMTAG3,
7171
FEAT_SB,
7272
FEAT_PREDRES,
73-
FEAT_SSBS,
73+
RESERVED_FEAT_SSBS, // previously used and now ABI legacy
7474
FEAT_SSBS2,
7575
FEAT_BTI,
7676
RESERVED_FEAT_LS64, // previously used and now ABI legacy

‎compiler-rt/lib/builtins/cpu_model/aarch64/fmv/apple.inc‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -31,10 +31,6 @@ static bool isKnownAndSupported(const char *name) {
3131
}
3232

3333
static uint64_t deriveImplicitFeatures(uint64_t features) {
34-
// FEAT_SSBS2 implies FEAT_SSBS
35-
if ((1ULL << FEAT_SSBS2) & features)
36-
features |= (1ULL << FEAT_SSBS);
37-
3834
// FEAT_FP is always enabled
3935
features |= (1ULL << FEAT_FP);
4036

‎compiler-rt/lib/builtins/cpu_model/aarch64/fmv/mrs.inc‎

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -43,10 +43,8 @@ static void __init_cpu_features_constructor(unsigned long hwcap,
4343
setCPUFeature(FEAT_FCMA);
4444
if (hwcap & HWCAP_SB)
4545
setCPUFeature(FEAT_SB);
46-
if (hwcap & HWCAP_SSBS) {
47-
setCPUFeature(FEAT_SSBS);
46+
if (hwcap & HWCAP_SSBS)
4847
setCPUFeature(FEAT_SSBS2);
49-
}
5048
if (hwcap2 & HWCAP2_MTE) {
5149
setCPUFeature(FEAT_MEMTAG);
5250
setCPUFeature(FEAT_MEMTAG2);

‎llvm/include/llvm/TargetParser/AArch64CPUFeatures.inc‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -70,7 +70,7 @@ enum CPUFeatures {
7070
FEAT_MEMTAG3,
7171
FEAT_SB,
7272
FEAT_PREDRES,
73-
FEAT_SSBS,
73+
RESERVED_FEAT_SSBS, // previously used and now ABI legacy
7474
FEAT_SSBS2,
7575
FEAT_BTI,
7676
RESERVED_FEAT_LS64, // previously used and now ABI legacy

‎llvm/lib/Target/AArch64/AArch64FMV.td‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -81,8 +81,7 @@ def : FMVExtension<"sme", "FEAT_SME", "+sme,+bf16", 430>;
8181
def : FMVExtension<"sme-f64f64", "FEAT_SME_F64", "+sme,+sme-f64f64,+bf16", 560>;
8282
def : FMVExtension<"sme-i16i64", "FEAT_SME_I64", "+sme,+sme-i16i64,+bf16", 570>;
8383
def : FMVExtension<"sme2", "FEAT_SME2", "+sme2,+sme,+bf16", 580>;
84-
def : FMVExtension<"ssbs", "FEAT_SSBS", "", 490>;
85-
def : FMVExtension<"ssbs2", "FEAT_SSBS2", "+ssbs", 500>;
84+
def : FMVExtension<"ssbs", "FEAT_SSBS2", "+ssbs", 490>;
8685
def : FMVExtension<"sve", "FEAT_SVE", "+sve,+fullfp16,+fp-armv8,+neon", 310>;
8786
def : FMVExtension<"sve-bf16", "FEAT_SVE_BF16", "+sve,+bf16,+fullfp16,+fp-armv8,+neon", 320>;
8887
def : FMVExtension<"sve-ebf16", "FEAT_SVE_EBF16", "+sve,+bf16,+fullfp16,+fp-armv8,+neon", 330>;

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