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Pre-commit tests for PR adding more instruction to vlopt
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‎llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll

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Original file line numberDiff line numberDiff line change
@@ -3398,3 +3398,146 @@ define <vscale x 4 x double> @vfrec7(<vscale x 4 x float> %a) {
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%2 = call <vscale x 4 x double> @llvm.riscv.vfwmacc(<vscale x 4 x double> poison, <vscale x 4 x float> %a, <vscale x 4 x float> %1, iXLen 7, iXLen 6, iXLen 0)
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ret <vscale x 4 x double> %2
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}
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define <vscale x 4 x i32> @vandn_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {
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; CHECK-LABEL: vandn_vv:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
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; CHECK-NEXT: vandn.vv v10, v8, v10
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; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
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; CHECK-NEXT: vadd.vv v8, v10, v8
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; CHECK-NEXT: ret
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%1 = call <vscale x 4 x i32> @llvm.riscv.vandn.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)
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%2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)
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ret <vscale x 4 x i32> %2
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}
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define <vscale x 4 x i32> @vandn_vx(<vscale x 4 x i32> %a, i32 %b, iXLen %vl) {
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; CHECK-LABEL: vandn_vx:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a2, zero, e32, m2, ta, ma
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; CHECK-NEXT: vandn.vx v10, v8, a0
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; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
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; CHECK-NEXT: vadd.vv v8, v10, v8
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; CHECK-NEXT: ret
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%1 = call <vscale x 4 x i32> @llvm.riscv.vandn.nxv4i32.i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, i32 %b, iXLen -1)
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%2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)
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ret <vscale x 4 x i32> %2
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}
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define <vscale x 4 x i32> @vbrev_v(<vscale x 4 x i32> %a, iXLen %vl) {
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; CHECK-LABEL: vbrev_v:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
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; CHECK-NEXT: vbrev.v v10, v8
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; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
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; CHECK-NEXT: vadd.vv v8, v10, v8
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; CHECK-NEXT: ret
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%1 = call <vscale x 4 x i32> @llvm.riscv.vbrev.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen -1)
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%2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)
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ret <vscale x 4 x i32> %2
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}
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define <vscale x 4 x i32> @vclz_v(<vscale x 4 x i32> %a, iXLen %vl) {
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; CHECK-LABEL: vclz_v:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
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; CHECK-NEXT: vclz.v v10, v8
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; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
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; CHECK-NEXT: vadd.vv v8, v10, v8
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; CHECK-NEXT: ret
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%1 = call <vscale x 4 x i32> @llvm.riscv.vclz.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen -1)
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%2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)
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ret <vscale x 4 x i32> %2
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}
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define <vscale x 4 x i32> @vcpop_v(<vscale x 4 x i32> %a, iXLen %vl) {
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; CHECK-LABEL: vcpop_v:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
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; CHECK-NEXT: vcpop.v v10, v8
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; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
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; CHECK-NEXT: vadd.vv v8, v10, v8
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; CHECK-NEXT: ret
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%1 = call <vscale x 4 x i32> @llvm.riscv.vcpopv.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen -1)
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%2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)
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ret <vscale x 4 x i32> %2
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}
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define <vscale x 4 x i32> @vctz_v(<vscale x 4 x i32> %a, iXLen %vl) {
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; CHECK-LABEL: vctz_v:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
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; CHECK-NEXT: vctz.v v10, v8
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; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
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; CHECK-NEXT: vadd.vv v8, v10, v8
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; CHECK-NEXT: ret
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%1 = call <vscale x 4 x i32> @llvm.riscv.vctz.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen -1)
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%2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)
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ret <vscale x 4 x i32> %2
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}
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define <vscale x 4 x i32> @vror_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {
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; CHECK-LABEL: vror_vv:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
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; CHECK-NEXT: vror.vv v10, v8, v10
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; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
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; CHECK-NEXT: vadd.vv v8, v10, v8
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; CHECK-NEXT: ret
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%1 = call <vscale x 4 x i32> @llvm.riscv.vror.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)
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%2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)
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ret <vscale x 4 x i32> %2
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}
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define <vscale x 4 x i32> @vror_vx(<vscale x 4 x i32> %a, iXLen %b, iXLen %vl) {
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; CHECK-LABEL: vror_vx:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a2, zero, e32, m2, ta, ma
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; CHECK-NEXT: vror.vx v10, v8, a0
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; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
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; CHECK-NEXT: vadd.vv v8, v10, v8
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; CHECK-NEXT: ret
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%1 = call <vscale x 4 x i32> @llvm.riscv.vror.nxv4i32.iXLen(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen %b, iXLen -1)
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%2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)
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ret <vscale x 4 x i32> %2
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}
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define <vscale x 4 x i32> @vror_vi(<vscale x 4 x i32> %a, iXLen %vl) {
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; CHECK-LABEL: vror_vi:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
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; CHECK-NEXT: vror.vi v10, v8, 5
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; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
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; CHECK-NEXT: vadd.vv v8, v10, v8
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; CHECK-NEXT: ret
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%1 = call <vscale x 4 x i32> @llvm.riscv.vror.nxv4i32.iXLen(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen 5, iXLen -1)
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%2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)
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ret <vscale x 4 x i32> %2
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}
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define <vscale x 4 x i32> @vrol_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl) {
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; CHECK-LABEL: vrol_vv:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
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; CHECK-NEXT: vrol.vv v10, v8, v10
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; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
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; CHECK-NEXT: vadd.vv v8, v10, v8
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; CHECK-NEXT: ret
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%1 = call <vscale x 4 x i32> @llvm.riscv.vrol.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen -1)
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%2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)
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ret <vscale x 4 x i32> %2
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}
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define <vscale x 4 x i32> @vrol_vx(<vscale x 4 x i32> %a, iXLen %b, iXLen %vl) {
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; CHECK-LABEL: vrol_vx:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a2, zero, e32, m2, ta, ma
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; CHECK-NEXT: vrol.vx v10, v8, a0
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; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
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; CHECK-NEXT: vadd.vv v8, v10, v8
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; CHECK-NEXT: ret
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%1 = call <vscale x 4 x i32> @llvm.riscv.vrol.nxv4i32.iXLen(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen %b, iXLen -1)
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%2 = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %1, <vscale x 4 x i32> %a, iXLen %vl)
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ret <vscale x 4 x i32> %2
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}

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